LPC_SYSCON_TypeDef::SYSTICKCLKDIV

[lpcware]

Content originally posted in LPCWare by rkiryanov on Tue Feb 16 06:25:05 MST 2010
Hello,

subj is listed in LPC11xx.h but not listed in UM. Is it used in LPC111x?

Thanks.

[lpcware]

Content originally posted in LPCWare by NXP_USA on Tue Feb 23 02:29:20 MST 2010

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Quote: rkiryanov
UM, Chapter 15: LPC111x System tick timer, 6. Example timer calculations


Why 1/2 AHBCLK?

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Sorry about that- the LPC1114 SYSCLK runs at AHBCLK on the LPC1114 and does not have a it is the same, just no pre-divider like the LPC1343. There is no additional /2.

-NXP

[lpcware]

Content originally posted in LPCWare by rkiryanov on Tue Feb 23 01:57:58 MST 2010

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Quote: NXP_USA
1/2 the AHBCLK

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UM, Chapter 15: LPC111x System tick timer, 6. Example timer calculations

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Quote:
Example (system clock = 50 MHz)
RELOAD = (system clock frequency × 10 ms) - 1 = (50 MHz × 10 ms) - 1 = 500000 - 1 = 499999 = 0x0007A11F

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Why 1/2 AHBCLK?

[lpcware]

Content originally posted in LPCWare by NXP_USA on Tue Feb 23 01:29:43 MST 2010

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Quote: rkiryanov
Hello,

subj is listed in LPC11xx.h but not listed in UM. Is it used in LPC111x?

Thanks.

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In the LPC1300 parts the AHBCLK is divided by SYSTICKCLKDIV to drive the Systick timer.

In the LPC1100 parts, Systick is always clocked by the AHBCLK. [email revised by NXP]

-NXP

[lpcware]

Content originally posted in LPCWare by brucesegal on Wed Feb 17 09:38:32 MST 2010
Yes the change notes for version 10 of the UM state:

• Systick chapter updated. • Systick clock divider removed from syscon block.

amongst other changes.

So I guess the CMSIS will update eventually

[lpcware]

Content originally posted in LPCWare by noritan_org on Tue Feb 16 07:03:29 MST 2010
The register have exist in the Rev.00.09 revision of UM10398 user manual. But, in the Rev.00.10 revision, it is disappeared.

It seems that there is an 8-bit R/W register at the address 0x400480b0, but it does not affect to the operation of SysTick.