Interrupts are themselves interruptable?

[lpcware]

Content originally posted in LPCWare by menhwa on Tue Mar 06 00:48:15 MST 2012
With LPC1113/302, I has enabled two interrupts source: I2C interrupt and 32-bit timer0 interrupt.

If I set I2C interrupt as priority 0, and 32-bit Timer0 interrupt as priority 1. During serving of 32-bit Timer0 interrupt, if I2C interrupt is triggered, will the timer0 interrupt been halted and serve the I2C interrupt? Or I2C interrupt only been served after the 32-bit interrupt?

Sorry as I confuse with the concept. Thanks.

[lpcware]

Content originally posted in LPCWare by gbm on Tue Mar 06 01:20:23 MST 2012
Cortex M has preemptive multilevel interrupts. An interupt will interrupt another if it's priority is logically higher (numerically lower) than the currently-servicd one. Initially all priorities are set as highest - 0.

All of this is descibed in ARM manuals and in a section on Cortex M core in NXP manual.