Content originally posted in LPCWare by LynnF on Wed Apr 14 17:25:28 MST 2010
Can someone please offer an explanation of the following, please.
Edge sensitive is obvious but what is "level sensitive"? I would assume a steady state has been reached, and if correct how long is the steady state before the interrupt is generated?
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[LEFT][/SIZE][/FONT][B][FONT=Arial][SIZE=1][COLOR=#005042][FONT=Arial][SIZE=1][COLOR=#005042][FONT=Arial][SIZE=1][COLOR=#005042]Table 111. GPIOnIS register (GPIO0IS, address 0x5000 8004 to GPIO3IS, address 0x5003[/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][/B][FONT=Arial][SIZE=1][COLOR=#005042][FONT=Arial][SIZE=1][COLOR=#005042]
[B][SIZE=1][FONT=Arial][COLOR=#005042]8004) bit description[/COLOR][/FONT][/SIZE][/B]
[/COLOR][/SIZE][/FONT][/COLOR][/SIZE][/FONT][B][FONT=Arial][SIZE=1][FONT=Arial][SIZE=1]Bit Symbol Access Value Description Reset[/SIZE][/FONT][/SIZE][/FONT][/B][FONT=Arial][SIZE=1]
[B][SIZE=1][FONT=Arial]value[/FONT][/SIZE][/B]
[/SIZE][/FONT][FONT=Arial][SIZE=1][FONT=Arial][SIZE=1]11:0 ISENSE R/W Selects interrupt on pin x as level or edge sensitive[/SIZE][/FONT]
[SIZE=1][FONT=Arial](x = 0 to 11).[/FONT][/SIZE]
[SIZE=1][FONT=Arial]0x00[/FONT][/SIZE]
[SIZE=1][FONT=Arial]0 Interrupt on pin PIOn_x is configured as edge[/FONT][/SIZE]
[SIZE=1][FONT=Arial]sensitive.[/FONT][/SIZE]
[SIZE=1][FONT=Arial]1 Interrupt on pin PIOn_x is configured as [COLOR=red]level[/COLOR][/FONT][/SIZE]
[SIZE=1][FONT=Arial][COLOR=red]sensitive.[/COLOR][/FONT][/SIZE][/LEFT]
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