Instruction & Clock execution times

[lpcware]

Content originally posted in LPCWare by deBoogle on Sun Feb 20 04:45:49 MST 2011
Hi there,

Does anyone know of creating a very small (10ns) delay. By my calculations one instruction (depending on actual instrction) should take 10ns with CPU = 100MHz.  So I figured use asm and put in a NOP.  But some sources I have read suggest this may be removed from instruction pipeline by the CPU.
I have seen the __NOP() function in the CMIS coreM3.h file, but this still uses quite a few (5 or 6) instructions to do the stack pushing and popping.  Is it safe for me just to put in an inline asm NOP??

As an aside is there anyway of counting total clk cycles used in a delay within LPCXpresso? I have been stepping through the instructions, but the questions is, is one step = 1 clk cycle??? I think it is more likely 1 step = 1 instrction execution regardless of clk cycles used to execute said instruction.


thanks
deBoogle

[lpcware]

Content originally posted in LPCWare by deBoogle on Sun Feb 20 06:41:32 MST 2011
What do you mean by 'don't use a NOP behind another NOP'?

Do you mean don't use two consecutively?

thanks for the quick response by the way.

deBoogle

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Sun Feb 20 06:23:24 MST 2011
Just use

__ASM volatile ("nop");

without branch, push, pop it delays 10ns.

You can use

Core Register -> Cycle

to count cycles.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337g/DDI0337G_cortex_m3_r2p0_trm.pdf

describes that timing isn't as easy as in good old 8051 times:

[LEFT][B][FONT=Helvetica-Bold]18.1 About instruction timing[/FONT][/B]
[FONT=Times-Roman][SIZE=2][FONT=Times-Roman][SIZE=2]The timing information in this chapter covers each instruction in addition to interactions[/SIZE][/FONT][/SIZE][/FONT][FONT=Times-Roman][SIZE=2]
[SIZE=2][FONT=Times-Roman]between instructions. It also contains information about factors that influence timings.[/FONT][/SIZE]
[SIZE=2][FONT=Times-Roman]When looking at timings, it is important to understand the role that the system[/FONT][/SIZE]
[SIZE=2][FONT=Times-Roman]architecture plays. Every instruction must be fetched and every load/store must go out[/FONT][/SIZE]
[SIZE=2][FONT=Times-Roman]to the system. These factors are described along with intended system design, and the[/FONT][/SIZE][/LEFT]
[SIZE=2][FONT=Times-Roman]implications for timing.[/FONT][/SIZE]


[/SIZE][/FONT]So I would suggest to measure this delay with a scope.

Note: Don't use a nop behind another nop, this doesn't work. You also get a 10ns delay.