GPIO masked access

lpcware · ‎06-15-2016

Content originally posted in LPCWare by mhjerde on Thu Nov 04 04:48:23 MST 2010
Hi

I need to set and clear a pin very quickly. I seems like the way to directly set a pin is to use masked access? Masked access is mentioned at page 124 of the 1343 UM, but I can't get my head around it.

This is what I do now:

if (val!= 0){                            //val is either 0 or 1
        LPC_GPIO1->DATA     |= (1 << 8);    // set pin 8 high
    } else {
        LPC_GPIO1->DATA     &= ~(1 << 8);    // set pin 8 low

Can I set pin 8 to the value of val directly via masked access, and if so, could someone shed some light on the syntax?

Cheers
Morten

lpcware · ‎06-15-2016

Content originally posted in LPCWare by stalisman on Fri Mar 23 02:38:57 MST 2012

Quote: KimLui
I tried [LPC_GPIO0->MASKED_ACCESS[ BIT_MASK ] = address;] on LPC1227,
when I build program,it reply:
'LPC_GPIO_Type' has no member named 'MASKED_ACCESS' main.c

I find many example about M0, All used Masked_access,
Why I can't use it?

Hi,

I have been trying to understand how 'masked access' works and it is quite unexpectedly wierd, it's a bit like talking to a geek who will only tell you the right answer if you ask the right question ... it can hide information in other words.

Anyway, It seems that Masked Access is not available on the LPC12xx family in the way it is used on the LPC11xx and LPC13xx families.

MASK and MASKED_ACCESS are not different spellings for the same thing, they are entirely different and so different solutions will be needed on the LPC1227. What those solutions are I do not know at the moment so this thread is still open as far as I can see.

So where to go?

'Masked Access' is functionality of The Cortex M, whilst 'MASKED_ACCESS' is a software artifact introduced to provide 'C-like Memory'access to the exotic hardware of the AHB GPIO.

Not only is it not memory it does not act like memory and can be quite dangerous in the hands of a novice if multiple bits are set and cleared. Why? because, at a later date, a different engineer to the orignal codewriter will see a uint32_t containing the states of certain gpio bits and will not know which ones are valid and which ones are not. (If documentation were perfect such would not be the case but this is the real world :-) )

Now I have only been looking at this since yesterday and so at the moment all I can suggest is following section 3.5.1 of the following document:
[COLOR=#5174a3]http://infocenter.arm.com/help/topic...t_r0p0_trm.pdf[/COLOR]

I didn't even find any help in the so called Definitive guide to the Cortex M0 which suggests that this is a murky topic.

Best Regards

Stali

lpcware · ‎06-15-2016

Content originally posted in LPCWare by stalisman on Fri Mar 23 02:36:24 MST 2012
Hi,

I have been trying to understand how 'masked access' works and it is quite unexpectedly wierd, it's a bit like talking to a geek who will only tell you the right answer if you ask the right question ... it can hide information in other words.

Anyway, It seems that Masked Access is not available on the LPC12xx family in the way it is used on the LPC11xx and LPC13xx families.

MASK and MASKED_ACCESS are not different spellings for the same thing, they are entirely different and so different solutions will be needed on the LPC1227. What those solutions are I do not know at the moment so this thread is still open as far as I can see.

So where to go?

'Masked Access' is functionality of The Cortex M, whilst 'MASKED_ACCESS' is a software artifact introduced to provide 'C Memory like' access to the exotic hardware of the AHB GPIO.

Not only is it not memory it does not act like memory and can be quite dangerous in the hands of a novice of multiple bits are set and cleared. Why? because at some stage a different engineer to the orignal codewriter will see a uint32_t containing the states of certain gpio bits and will not know which ones are valid and which ones are not. (If documentation were perfect such would not be the case but this is the real world :-) )

Now I have only been looking at this since yesterday and so at the moment all I can suggest is following section 3.5.1 of the following document:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0479b/DDI0479B_cortex_m_system_design_kit_r0p0_t...

I din't even find any help in the so called Definitive guide to the Cortex M0 which suggests that this is a murky topic.

Best Regards

Stali

lpcware · ‎06-15-2016

Content originally posted in LPCWare by atomicdog on Tue Feb 28 10:29:54 MST 2012
Here's another way...

// WRITE
#define SET_PIN(port,pin)      LPC_GPIO##port->MASKED_ACCESS[(1<<pin)] = (1<<pin)
#define CLEAR_PIN(port,pin)    LPC_GPIO##port->MASKED_ACCESS[(1<<pin)] = 0
#define SET_PORT(port,pins,val)  LPC_GPIO##port->MASKED_ACCESS[pins] = val

// READ
#define GET_PIN(port,pin)      LPC_GPIO##port->MASKED_ACCESS[(1<<pin)]
#define GET_PORT(port,pins)    LPC_GPIO##port->MASKED_ACCESS[pins]

SET_PIN(2,1);//-Set pin One of Port Two

lpcware · ‎06-15-2016

Content originally posted in LPCWare by OA santana on Tue Feb 28 03:21:37 MST 2012
I solved the rude way by replacing

#define CLEAR_LED(x) {GPIO_SetLowLevel(LPC_GPIO2 , x, 1);}

for

#define CLEAR_LED(x) { *(uint32_t *)0x50020010 = (1<<x);}

Where 0x50020010 is the data register's address

Hope this helped you.
Best Regards.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by KimLui on Tue Feb 14 23:35:10 MST 2012

Quote: atomicdog
Look in the header file that defines [I]LPC_GPIO0[/I] and you will see the member name is called [I]MASK[/I].

I think the "mask" is not same as masked_access[Bit_mask]:confused:

If I want define a 8bit port at GPIO2[16:8]

#define def_output LPC_GPIO2->masked_access[0xFF00]

How to use "mask" to do the same #define ?:confused:

lpcware · ‎06-15-2016

Content originally posted in LPCWare by atomicdog on Sun Feb 05 21:53:39 MST 2012

Quote: KimLui
I tried [LPC_GPIO0->MASKED_ACCESS[ BIT_MASK ] = address;] on LPC1227,
when I build program,it reply:
'LPC_GPIO_Type' has no member named 'MASKED_ACCESS' main.c

I find many example about M0, All used Masked_access,
Why I can't use it?

Look in the header file that defines [I]LPC_GPIO0[/I] and you will see the member name is called [I]MASK[/I].

lpcware · ‎06-15-2016

Content originally posted in LPCWare by KimLui on Sun Feb 05 21:12:11 MST 2012
I tried [LPC_GPIO0->MASKED_ACCESS[ BIT_MASK ] = address;] on LPC1227,
when I build program,it reply:
'LPC_GPIO_Type' has no member named 'MASKED_ACCESS'main.c

I find many example about M0, All used Masked_access,
Why I can't use it?

lpcware · ‎06-15-2016

Content originally posted in LPCWare by fjrg76 on Thu Nov 03 23:06:11 MST 2011

Quote: Skashkash
I just started working with masked access yesterday.
It's pretty simple using the CMSIS structure

Just create a bit mask for the pins in question.

#define BIT_MASK 0x07 // we only want the lower three bits

// now output your data via the bit mask
LPC_GPIO0->MASKED_ACCESS[ BIT_MASK ] = address;

Only the lower 3 bits of address will actually be copied to GPIO0.0 through GPIO0.2, all the other pins remain unaffected.

Note that the bits in the mask can be non continuous.

Bit banding might be faster, but it appears that the 1343 does not have bit banding for the IO ports. I'm still looking into that, and would be happy to be proven wrong.

Hi

I got a doubt while reading this entry, but after looking at the user manual (LPC1114) I have answered myself, so I'll post my thoughts just in case someone else gets the same doubt:

[B]Doubt[/B]: The LPC_GPIO_TypeDef CMSIS structure is 4096 words!! So, if you declare a variable of this type, you'll waste 4096 words of the valuable SRAM, right?

[B]Answer[/B]: Wrong!! When one declares a variable of LPC_GPIO_TypeDef type, the variable is mapped into the GPIO's peripheral memory map in the AHB bus, so not a single byte in user's SRAM is touched. I can imagine the AHB memory region as very special and exclusive kind of RAM, in which the user has no rights to use it, but only for the peripheral's convenience.

In fact, 4 variables of LPC_GPIO_TypeDef type are declared, one for each GPIO port.

LPC11xx.h excerpt
[FONT=Courier New]...
/* AHB peripherals */
#define LPC_GPIO_BASE         (LPC_AHB_BASE + 0x00000)
#define LPC_GPIO0_BASE        (LPC_AHB_BASE + 0x00000)
#define LPC_GPIO1_BASE        (LPC_AHB_BASE + 0x10000)
#define LPC_GPIO2_BASE        (LPC_AHB_BASE + 0x20000)
#define LPC_GPIO3_BASE        (LPC_AHB_BASE + 0x30000)
...
#define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
#define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
#define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
#define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
...
[/FONT]

Greetings

lpcware · ‎06-15-2016

Content originally posted in LPCWare by CodeRedSupport on Thu Nov 04 06:34:08 MST 2010
Re bitbanding:
LPC13xx does not have bitbanding. See this thread:
http://knowledgebase.nxp.com/showthread.php?t=627

lpcware · ‎06-15-2016

Content originally posted in LPCWare by CodeRedSupport on Thu Nov 04 06:20:51 MST 2010
There is some example code showing how to use masked access in the GPIOSetValue() function in gpio.c in the LPC13xx_Lib project from the LPCXpresso1343.zip file in <install_dir>\Examples\NXP\LPC1000\LPC13xx.

I think that in the more extensive, NXP maintained examples, a slight variation of this is provided as an inline function in gpio.h.

Regards,
CodeRedSupport

lpcware · ‎06-15-2016

Content originally posted in LPCWare by Skashkash on Thu Nov 04 06:17:12 MST 2010
I just started working with masked access yesterday.
It's pretty simple using the CMSIS structure

Just create a bit mask for the pins in question.

#define BIT_MASK 0x07 // we only want the lower three bits

// now output your data via the bit mask
LPC_GPIO0->MASKED_ACCESS[ BIT_MASK ] = address;

Only the lower 3 bits of address will actually be copied to GPIO0.0 through GPIO0.2, all the other pins remain unaffected.

Note that the bits in the mask can be non continuous.

Bit banding might be faster, but it appears that the 1343 does not have bit banding for the IO ports. I'm still looking into that, and would be happy to be proven wrong.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by mhjerde on Thu Nov 04 05:43:24 MST 2010
Thanks
I am trying to avoid the if/else construct, as this bit of code is driving a display. So I want max speed and I was hoping masked access would let me set the pin directly. Something like

GPIOn_masked access[pin] = value

It looks like this is possible, but I don't understand how it is done.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by NXP_Europe on Thu Nov 04 05:20:12 MST 2010
Hello mhjerde,

setting a bit:
LPC_GPIO1->DATA |= (1 << 8); ... is binairy 1 0000 0000
in other words ... DATA |= ... 1 0000 0000 (bit 8 becomes high)

resetting a bit:
LPC_GPIO1->DATA &= ~(1 << 8); ... is binairy 0 1111 1111
in other words ... DATA &= ... ~(1<<8) is ~1 0000 0000 is 0 1111 1111
All bits are kept the same exept bit number 8. It becomes low.