Content originally posted in LPCWare by MikeSimmonds on Thu Dec 05 00:38:25 MST 2013
In another thread (sorry, I can't be bothered to find it -- use search) NXP say SYSRESETREQ *IS* supported on 176x, and I know that it works on 1778 which is used in my design.
However, there *may* be an issue when the ethernet module is involved ...
When the internal reset happens (SYSRESETREQ) there is a low level pulse on the reset out pin -- just the same as with a
power on reset *BUT* it is very short -- IIRC, about 1.25 microseconds.
Most ethernet designs feed the reset out to the PHY chip's reset input, but the reset duration is nowhere near long enough.
Therefore the PHY chip is not reset properly and when you come to initialise the internal ethernet MAC module the 1778
hangs AND looses the debug connection! There is a footnote in the UM10470 about the lack of a valid ethernet reference
clock freezing the chip when you access the ethernet MAC module.
Hope this is of interrest, Mike