Default values for PLL0CFG_Val?

[lpcware]

Content originally posted in LPCWare by piperazine on Sun Apr 10 02:27:20 MST 2011
Hello,

Ive got a LPCXpresso1769 board, and a little curious about values PLL0CFG_Val. I noticed that in system_LPC17xx.c the value is set to 0x00050063 with a clock divide of 4 (CCLKCFG_Val 0x00000003):
Fcco = (2*12*100)/6 = 400
400/clock divide(4) = 100Mhz

and the manual says:

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Quote:
"A smaller value for the PLL pre-divide (N) as well as a smaller value of the multiplier (M),
both result in better PLL operational stability and lower output jitter. Lower values of FCCO
also save power."

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Is there a reason for setting the M and N values so high there? Wouldn't setting PLL0CFG_Val to 0x00010018 and clock divide to 3 (CCLKCFG_Val 0x00000002) be better?
Fcco = (2*12*25)/2 = 300
300/clock divide(3) = 100Mhz

I know the LPC1769 can run at 120Mhz, but I was wondering why these values were chosen for 100Mhz operation? For a 120Mhz clock I was going to set PLL0CFG_Val to 0x0000000E and CCLKCFG_Val to 0x00000002:
Fcco = (2*12*15)/1 = 360
360/clock divide(3) = 120Mhz

Do these values seem correct?

[lpcware]

Content originally posted in LPCWare by larryvc on Sun Apr 10 12:05:25 MST 2011
I'll give that a try.

I remembered that when I tried the other values I was using an LPCXpresso 1769 that had some missing components for the RTC.  Maybe there were other issues with that board.  EA replaced the board so I will also try some other values just for grins.

Thanks

[lpcware]

Content originally posted in LPCWare by jharwood on Sun Apr 10 11:29:10 MST 2011
FWIW, my board is running fine with:

PLL0CFG_Val to 0x00000013 and CCLKCFG_Val to 0x00000003:
Fcco = (2*12*20)/1 = 480
480/clock divide(4) = 120Mhz

[lpcware]

Content originally posted in LPCWare by larryvc on Sun Apr 10 11:12:19 MST 2011
Even when the PLL calculator indicated a good value at the lower values of FCCO I had some problems using them.  It's been a while since I tried them and don't recall exactly what values I tried or what the problems were.  I will try to provide more details on this as soon as I get the time to do so.

It may have been when I was trying the NXP examples with the wrong version of CMSISv2 (contains version 1.2 files).

TAX TIME!!!:(

[lpcware]

Content originally posted in LPCWare by piperazine on Sun Apr 10 10:55:10 MST 2011
Thanks mate, I checked the values on the spreadsheet and they looked ok. I've left my board at work so I've got no way of checking it at the moment, but I'm sure it'll work. I was just a bit confused to why the default M and N values in CMSIS lib were so high (100 & 6). I stumbled upon this in the CMSIS history text file which could explain it:

---

Quote:
"23 March 2010
-------------
system_LPC17xx.c updated to new version (1.07, dated 12 February
2010) - with fix to check on value of CCLKCFG_Val to remove need
for it to be odd only."

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So I'm guessing the values used are because of when CCLKCFG_Val needed to be odd perhaps :confused:

[lpcware]

Content originally posted in LPCWare by larryvc on Sun Apr 10 09:49:47 MST 2011
Have you seen the LPC17xx PLL Calculator (Microsoft Excel)

http://ics.nxp.com/support/documents/microcontrollers/xls/lpc17xx.pll.calculator.xls

[lpcware]

Content originally posted in LPCWare by jharwood on Sun Apr 10 09:43:46 MST 2011

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Quote: piperazine
For a 120Mhz clock I was going to set PLL0CFG_Val to 0x0000000E and CCLKCFG_Val to 0x00000002:
Fcco = (2*12*15)/1 = 360
360/clock divide(3) = 120Mhz

Do these values seem correct?

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Yes, those look spot on. I  downloaded an LPC17xx.pll.calculator.xls spreadsheet from somewhere which confirms your settings. I'll see if I can find a link to it.

edit: found it right here