DMA Request source - DMAREQSEL

[lpcware]

Content originally posted in LPCWare by akharsa on Wed Feb 23 11:19:07 MST 2011
Hello,
I'm working on a DSP design in wich I need to make use of the ADC along with DMA and also de DAC.

The first problem I got was getting a correct sampling freq at de ADC. With the DAC I can make this using the counter and generating requests from de DAQ. But with the ADC this is not possible.

I was told that a good idea was to use a TIMER Match to generate de requests. For making this, i setup de TIMER and generates de requests. But the DMAREQSEL bit must be '1' for the request to select between MAT0.0 and UART. Obviously I need MAT0.0

The problem is thath the following line:

DMAREQSEL |= 0x01;

Doesn't change de actual value of the register DMAREQSEL (0x4000C1C4). If I pause the debugger and then check for the value of DMAREQSEL it shows me 0x00. But if I manually change this value in the memory watch monitor to 0x01, request are generated but after this te value is again set to 0x00. It seems that my code doesn't update te value.

Does anyone get this type of behaivour?

Thanks in advance,
Alan

[lpcware]

Content originally posted in LPCWare by ahaczewski on Sat Feb 26 14:18:15 MST 2011
As far as I can tell DMAREQSEL is at 0x400FC1C4. DMAREQSEL register is in System Control part of memory. You should be able to get to DMAREQSEL using this structure:

typedef struct
{
  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */
       uint32_t RESERVED0[31];
  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
  __IO uint32_t PLL0CFG;
  __I  uint32_t PLL0STAT;
  __O  uint32_t PLL0FEED;
       uint32_t RESERVED1[4];
  __IO uint32_t PLL1CON;
  __IO uint32_t PLL1CFG;
  __I  uint32_t PLL1STAT;
  __O  uint32_t PLL1FEED;
       uint32_t RESERVED2[4];
  __IO uint32_t PCON;
  __IO uint32_t PCONP;
       uint32_t RESERVED3[15];
  __IO uint32_t CCLKCFG;
  __IO uint32_t USBCLKCFG;
  __IO uint32_t CLKSRCSEL;
  __IO uint32_tCANSLEEPCLR;
  __IO uint32_tCANWAKEFLAGS;
       uint32_t RESERVED4[10];
  __IO uint32_t EXTINT;                 /* External Interrupts                */
       uint32_t RESERVED5;
  __IO uint32_t EXTMODE;
  __IO uint32_t EXTPOLAR;
       uint32_t RESERVED6[12];
  __IO uint32_t RSID;                   /* Reset                              */
       uint32_t RESERVED7[7];
  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
  __IO uint32_t PCLKSEL0;
  __IO uint32_t PCLKSEL1;
       uint32_t RESERVED8[4];
  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
  __IO uint32_t DMAREQSEL;              /* DMA Request Select register        */
  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
 } LPC_SC_TypeDef;

Note that according to some docs I've found Keil doesn't define DMAREQSEL in LPC_SC struct, and NXP recommends adding it like above. According to that doc DMAREQSEL is RESERVED9, like:

[...snip...]
  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
  __IO uint32_t RESERVED9;
  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
 } LPC_SC_TypeDef;