Configure SSP Clock

[lpcware]

Content originally posted in LPCWare by andersonf on Wed May 25 05:29:31 MST 2011
Hello I need help!

What is the maximum amount of SSP clock that can work with the LPC1343
72Mhz?
SSP my clock is set to 4 MHz. Looking at the user manual data sheet
register Clock SSP0 Prescale Register - CPSDVSR is set to value 2.
This value is 2 to 254 .. and the greater is my slowest clock. One value can not be set!
Need to increase the clock SSP. which register / bit should I change?

Thanks!
Anderson

[lpcware]

Content originally posted in LPCWare by Ex-Zero on Wed May 25 05:55:45 MST 2011
Take a look at LPC_SSP->CR0 bit 8-15: SCR

SCR Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR × [SCR+1]).

With:

/* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR 0*/
  LPC_SSP->CR0 = 0x0007;

you should be able to run SSP up to 36MHz

Note: If you are using a standard LPC_SSP->CR0 = 0x0707; your CLOCK is 72MHz /2 / 8 = 4.5MHz