Content originally posted in LPCWare by MikeSimmonds on Thu Nov 08 08:22:54 MST 2012
[FONT=Tahoma][SIZE=1]On your page "[/SIZE][/FONT][FONT=Tahoma][SIZE=1]SWD / JTAG Connectors and Pinout", you recommend a 10K to 100K
pull-down to ground for SWCLK.
Various documents I have seen state that the SWD clock (SWCLK) is idle [I]high[/I].
So is this a mistake on your part, and the clock line is to be pulled [B]up[/B]? :confused:
Or is there something that I still do not understand?
Does this pull-up (or pull-down) apply to both the target board and the SWD adapter?
BTW: The LPCXpresso 1769 uses a tri-stated buffer for SWCLK idle (i.e. pull up)
and has [I]no[/I] pull ups or downs on the target side.
Please will you clarify/confirm the details, including the recommendations for
custom (SWD debugged) target boards.
Cheers, Mike.
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