lpc5528 set to slave i2s role

[harry3]

Hi nxp team,

I now need to set the I2S peripheral of the LPC5528 to slave mode. The I2S master role is provided by another MCU device. I have checked the LPC5528 example routines and found no method for setting I2S to slave mode. Could you please tell me how to configure the LPC5528 as an I2S slave?

thanks

harry 

[Harry_Zhang]

Hi @harry3 

You can refer to the SDK evkmimxrt685_i2s_interrupt_transfer demo.

It includes the i2s master and i2s master slave.

BR

Harry

[harry3]

hi zhang, After the i2s is set as the slave, all clock signals come from the external MCU. How should the mclk, bclk, and wsclk of i2s be configured? The clock in the example you provided comes from the 5528 itself, which is different from my schematic design. i2s做slave之后，时钟信号都是来自于外部的MCU。 i2s的mclk,bclk,wsclk要怎么配置呢？ 你举的这个例程的时钟是来自于5528自身，和我的图示设计是不同的。 thanks harry

[Harry_Zhang]

Hi @harry3 

Based on your need.

For the master(RT685), you can refer to the evkmimxrt685_i2s_interrupt_transfer_cm33 demo.

RT685 clock configuration can be maintained in demo mode.

RT685 (Master)  generate and output all three clocks: MCLK, BCLK (SCK), and WS (LRCLK).

For the slave(lpc55s28), you can refer to the lpcxpresso55s28_i2s_interrupt_transfer demo.

LPC55S28 (Slave)  receive these three clocks. Only MCLK needs explicit SYSCON configuration.

    /* Attach PLL clock to MCLK for I2S, no divider */
    CLOCK_AttachClk(kPLL0_to_MCLK);
    SYSCON->MCLKDIV = SYSCON_MCLKDIV_DIV(0U);
    SYSCON->MCLKIO  = 1U;

    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);
    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 1U, false);

    /*!< Switch PLL0 clock source selector to XTAL16M */
    /* I2S clocks */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM6);
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM7);

need modify  to 

    SYSCON->MCLKDIV = SYSCON_MCLKDIV_DIV(0U);
    SYSCON->MCLKIO  = 0U;

BCLK and WS do not require direction settings on LPC55S28; once the Flexcomm I2S is configured as Slave.

I think you can try it.

BR

Harry Zhang

[harry3]

你好Harry，

   非常感谢你的支持。

    先不讨论做主还是做从的问题，我请教一个关于channel的问题，在sdk例程中的有关DMA i2s的例程都是默认FC7做I2S TX，FC6做i2s RX,并且FC7共享时钟给FC6。对应的channel是tx对应19和rx对应16。它们之间的对应关系是怎么得到的呢？我试过把DEMO_I2S_TX_CHANNEL改成18，或导致EVK无法输出。说明它们之间的这个值是有对应逻辑关系的。这个关系在哪里可以找到？

thansk 

harry 

[Harry_Zhang]

Hi @harry3 

两个 MCU 之间的 I2S 直连，通常只需要 BCLK+ LRCLK+ SD（数据） 三根线，不需要 MCLK。Master产生 BCLK/WS，Slave按该时钟采样/发送数据。I2S 最初定义的就是“三线总线”，MCLK 并不是数据传输必须的信号。

MCLK 多见于 CODEC/ADC/DAC 等音频器件作为其内部过采样与数字滤波的参考时钟，对 MCU↔MCU 的 I2S 链路并非硬性要求。

如果你的RT685是master，BCLK+ LRCLK是由RT685产生。LPC55S28不需要产生BCLK+ LRCLK。

   /* Set flexcomm3 SCK, WS from shared signal set 0 */
    I2S_BRIDGE_SetFlexcommSignalShareSet(kI2S_BRIDGE_Flexcomm3, kI2S_BRIDGE_SignalSCK, kI2S_BRIDGE_ShareSet0);
    I2S_BRIDGE_SetFlexcommSignalShareSet(kI2S_BRIDGE_Flexcomm3, kI2S_BRIDGE_SignalWS, kI2S_BRIDGE_ShareSet0);

BR

Harry

[harry3]

hi harry 张，

谢谢你的支持

例程中用到I2S的共享，我看到的一般是有先设定源时钟到share0,在把share0 分配到电路对应的flexcomm组。例如下面这样

我做slave，是不是不需要按照上面方法配置SCLK和WS clk. 直接用两句SYSCTL_SetShareSet（...）;就可以了？

第二个问题，关于时钟，是不是在slave模式下不需要下图配置i2s的时钟部分。

thanks

harry