lpc 1788

[hedleydavidson]

The LPC 1788 datasheet / manual states that the rstout ( PIN 29 ) will go low on ANY reset ie wdt, por,reset input . When I look on the scope it only goes low on Reset Input 

Please clarify if , and how I can get it to go low on WDT - This is required to reset a PHY controller.

Reply's can be sent to hedley@cynaps.co.za or hedley.davidson@gmail.com

Thanks

[jeremyzhou]

Hi Hedley Davidson,

Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
In the LPCOpen library, it contains a periph_watchdog demo and you can run this demo to generate the watchdog reset, please give a try.
Have a great day,
TIC

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[hedleydavidson]

Thanks for reply . Perhaps my question was not clear . On the software side we have implemented embedded Linux with applications and watchdog code which all works . 

The problem / question. Is perhaps more related to the chip level and datasheet ie 

when the watchdog timer times out the RSTOUT pin does not go low . The only time this pin seems to go low is if the RESET in to the arm goes low ie it mirrors the reset in pin.

The datasheet says it will go low on ANY reset ??

[jeremyzhou]

Hi Hedley Davidson,
Thanks for your reply.
I've replicated the phenomenon, the WDT reset doesn't make the RESET_OUT pin go low like the external reset pin does.
I'd like to contact the AE team for confirming and will inform you later.
Have a great day,
TIC

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[hedleydavidson]

After more investigation the normal microcontroller issues apply.

1. The LPC 1788 does pulse the output for 1.6 uS following a watchdog timeout with our clock configuration 

2. The reason not seen on the scope is that we had this output driving a RC watchdog input to an Ethernet PHY. 

3. The Phy requires 60uS reset pulse which therefore needs a capacitor ie > 50 nF. 

4. This means that following reset the current drain on the RSTOUT pin exceeds the device capability . 

5. If the cap is changed for 1nf then the pulse can be clearly seen. 

A further difficulty is that as soon as the processor has reset it starts u-boot and then Linux . In u- boot the processor tries to talk to the PHY which is not yet ready as the PHY reset time is > than the cpu. The result is that u-boot can not complete and the system hangs . The end product is electronic access control doing millions of transactions per month so an edge device hanging causes extreme end user frustration as you can’t open the door . 

The only way I found this was to simulate the schematic on LTSPICE . 

And spend a full day testing . 

Now the problem is defined the next step is to design a pulse stretcher and also change u-boot to have a 100ms delay on startup.