i2C_polling_b2b_master SDK examples creates 741 KHZ SCL

[jtauch1]

We are using the LPC55evm and when we use the i2C_polling_b2b_master SDK example. The SCL clock frequency is wrong. It should be 100kHZ, instead, we see 741KHZ. Can someone explain the clock configuration for this example? 

Also is there a document that describes how the clocks are derived on this evm?

Thanks,

John

[xiangjun_rong]

Hi,

In the I2C master processor of LPC55xx, pls check the I2C clock source, I2C clock divider and SCL high/low time.

For example, you are using LPC55S69, pls refer to UM11126.pdf, I copy the part from UM11126.pdf.

I suggest you read the CLKDIV and MSTTIME registers, and the clock source selection FCCLKSELx register value, then use the formula to compute the I2C baud rate.

33.7.2.1 Rate calculations
Master timing
SCL high time (in Flexcomm Interface function clocks) =
I2C clock divider * SCL high multiplier, See Table 630 and Table 633
Nominal SCL rate =
Flexcomm Interface function clock rate / (SCL high time + SCL low time)

BTW, can you tell us the part number you are using?

Hope it can help you

BR

XiangJun Rong