clock generation for lcd controller block in LPC1788

[lpcware]

Content originally posted in LPCWare by hamedb3269 on Thu Feb 05 02:58:23 MST 2015
What is the role of the CLKSEL & BCD bits in the LCD_POL register?

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Mon Feb 09 12:34:57 MST 2015
CLKSEL selects the source for LCDCLK. 0 for CCLK and 1 for LCD_CLKIN.
Setting BCD to bypass the pixel clock divider logic.
UM10470 has more details on these registers.

http://www.lpcware.com/content/nxpfile/um10470-lpc178x7x-user-manual

regards,