about AHB MATRIX connection

[lpcware]

Content originally posted in LPCWare by uratan on Sat Dec 22 05:12:36 MST 2012
Hi, please anyone solve my question ?

In Fig.1 (page 12, UM10430, Rev.2.1),
  there are multiple BRIDGEs between AHB MULTILAYER MATRIX and (APB) peripherals.
In Fig.7 (page 23),
  there is only one horizontal line for (APB) peripherals.

It means that there is only one slave channel for all peripherals ?
<PRE>
   AHB MATRIX   |
                |
...------------|----+--- BRIDGE1 --- periphs1
                |    +--- BRIDGE2 --- periphs2
----------------+    +--- BRIDGE3 --- periphs3
                     +--- ...
</PRE>


  (Sat Dec 22 21:10:35 JST 2012)

[lpcware]

Content originally posted in LPCWare by uratan on Sat Jan 12 22:51:32 MST 2013
Thank you very much to solve my question.

I am able to be convinced that it was designed to give priority to a performance.

<PRE>
   AHB MATRIX   |
                |
...------------|----BRIDGE0 --- periphs0 ... UART1
                |
...------------|----BRIDGE1 --- periphs1 ... ...
                |
...------------|----BRIDGE2 --- periphs2 ... USART3
            .   |      .
            .   |      .
            .   |      .
----------------+
</PRE>


  - * - * -



One report about UM10430(Rev2.1)

Only 8 IPRn registers are described in Table 20 but the chip must have more.

And it is better, I think, if the bitmap is described,


<PRE>
+-----------+
| 7654 3210 |
+-----------+
| nnn0 0000 | (lower 5bits are un-implemented, fixed to 0)
+-----------+
</PRE>
and mentioned about AIRCR.
(Users can seek Cortex-M3 manuals for AIRCR)



  (Sun Jan 13 14:50:25 JST 2013)

[lpcware]

Content originally posted in LPCWare by nxp21346 on Fri Jan 11 17:38:59 MST 2013
Hi!

Each block of AHB peripherals has a separate slave channel on the matrix so there should be no contention accessing for example, UART1 via the M3 core and USART3 via the GPDMA.

-Dave @ NXP