Why is Chip_EEPROM_Write() not implemented for LPC43xx

[javiervallori]

Hi,

the function Chip_EEPROM_Write() and Chip_EEPROM_Read() is declared in the header file eeprom.h of the LPCOpen for LPC 43xx version 3.01, but there are no implementation for it. Why? Where can I found it?

[javiervallori]

How do you use the LPC_EEPROM->AUTOPROG register in the write opertations?

[javiervallori]

Yes, by default all the clocks start enable after reset, and I disable the ones I don't need in order to reduce consumption. The EEPROM works, I have some products in production with strong use of EEPROM, and works well. The chip model I use is the LPC4337.

[nxp68994]

Hi Javier,

In your listing you disable all clocks. What is not disabled explicitly is enabled?

Hmmm. The reset value of the clock configuration register is 1. This means the clock is enabled by default after reset! This is not what I expected. Anyhow, you disable all peripherals which are not needed and the EEPROM works for you?

I will check it out.

Thank you for bumping me into this strange “clock enable” behavior.

[nxp68994]

Hi Javier,

Thank you for responding!

This would be very helpful if you share the fragment where you setup the EEPROM.

I call Chip_EEPROM_Init(), write the bytes to the first page 0x20040000 and finally I call Chip_EEPROM_EraseProgramPage() to program the bytes (I use only the first 128 bytes). In my approach, every word written to 0x20040000 has no effect. It means if I read the word, I always get 0x00000000. Therefore, I assume something in Chip_EEPROM_Init() is missing.

I am curious where the mistake is in my approach.

Thank you Javier in advance.

[javiervallori]

Hi Wolfgang,

I don't do any kind of setup on the EEPROM, in fact I don't even call the Chip_EEPROM_Init() (and maybe I should :O). Perhaps your problem is related with the system clocks, do you disable any of them? I pass the code where I disable some of them. Check wich ones I leave enable. Of course CLK_MX_EEPROM, also but CLK_PERIPH_BUS, CLK_PERIPH_CORE, CLK_MX_BUS, CLK_MX_MXCORE.

  uint32_t ii;

    //CLK_BASE_SAFE Allways on


    Chip_Clock_DisableBaseClock(CLK_BASE_USB0);


    //Chip_Clock_DisableBaseClock(CLK_BASE_PERIPH);
            //Chip_Clock_Disable(CLK_PERIPH_BUS);        /*!< Peripheral bus clock from base clock CLK_BASE_PERIPH */
            //Chip_Clock_Disable(CLK_PERIPH_CORE);        /*!< Peripheral core clock from base clock CLK_BASE_PERIPH */
            //Chip_Clock_Disable(CLK_PERIPH_SGPIO);        /*!< SGPIO clock from base clock CLK_BASE_PERIPH */



    Chip_Clock_DisableBaseClock(CLK_BASE_USB1);


    CHIP_CCU_CLK_T chips_cloks_MX [] = {
            //CLK_MX_BUS,        /*!< M3/M4 BUS core clock from base clock CLK_BASE_MX */
            CLK_MX_SPIFI,        /*!< SPIFI register clock from base clock CLK_BASE_MX */
            //CLK_MX_GPIO,        /*!< GPIO register clock from base clock CLK_BASE_MX */
            CLK_MX_LCD,            /*!< LCD register clock from base clock CLK_BASE_MX */
            CLK_MX_ETHERNET,    /*!< ETHERNET register clock from base clock CLK_BASE_MX */
            CLK_MX_USB0,        /*!< USB0 register clock from base clock CLK_BASE_MX */
            CLK_MX_EMC,            /*!< EMC clock from base clock CLK_BASE_MX */
            CLK_MX_SDIO,        /*!< SDIO register clock from base clock CLK_BASE_MX */
            CLK_MX_DMA,            /*!< DMA register clock from base clock CLK_BASE_MX */
            //CLK_MX_MXCORE,        /*!< M3/M4 CPU core clock from base clock CLK_BASE_MX */
            //RESERVED_ALIGN,
            //CLK_MX_SCT,        /*!< SCT register clock from base clock CLK_BASE_MX */
            CLK_MX_USB1,        /*!< USB1 register clock from base clock CLK_BASE_MX */
            CLK_MX_EMC_DIV,        /*!< ENC divider clock from base clock CLK_BASE_MX */
            //CLK_MX_FLASHA,    /*!< FLASHA bank clock from base clock CLK_BASE_MX */
            //CLK_MX_FLASHB,    /*!< FLASHB bank clock from base clock CLK_BASE_MX */
            CLK_M4_M0APP,        /*!< M0 app CPU core clock from base clock CLK_BASE_MX */
            CLK_MX_ADCHS,        /*!< ADCHS clock from base clock CLK_BASE_ADCHS */
            //CLK_MX_EEPROM,    /*!< EEPROM clock from base clock CLK_BASE_MX */
            //CLK_MX_WWDT,        /*!< WWDT register clock from base clock CLK_BASE_MX */
            CLK_MX_UART0,        /*!< UART0 register clock from base clock CLK_BASE_MX */
            //CLK_MX_UART1,        /*!< UART1 register clock from base clock CLK_BASE_MX */    -> BLE
            CLK_MX_SSP0,        /*!< SSP0 register clock from base clock CLK_BASE_MX */
            //CLK_MX_TIMER0,        /*!< TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
            CLK_MX_TIMER1,        /*!< TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
            //CLK_MX_SCU,            /*!< SCU register/perigheral clock from base clock CLK_BASE_MX */
            //CLK_MX_CREG,        /*!< CREG clock from base clock CLK_BASE_MX */
            //CLK_MX_RITIMER,        /*!< RITIMER register/perigheral clock from base clock CLK_BASE_MX - For SyStimer */
            CLK_MX_UART2,        /*!< UART3 register clock from base clock CLK_BASE_MX */
            CLK_MX_UART3,        /*!< UART4 register clock from base clock CLK_BASE_MX */
            CLK_MX_TIMER2,        /*!< TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
            CLK_MX_TIMER3,        /*!< TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
            CLK_MX_SSP1,        /*!< SSP1 register clock from base clock CLK_BASE_MX */
            CLK_MX_QEI,            /*!< QEI register/perigheral clock from base clock CLK_BASE_MX */
    };
    for (ii = 0; ii < (sizeof(chips_cloks_MX)/sizeof(CHIP_CCU_CLK_T)); ii++) {
        Chip_Clock_Disable(chips_cloks_MX[ii]);
    }


    Chip_Clock_DisableBaseClock(CLK_BASE_SPIFI);
    Chip_Clock_DisableBaseClock(CLK_BASE_SPI);
    Chip_Clock_DisableBaseClock(CLK_BASE_PHY_RX);
    Chip_Clock_DisableBaseClock(CLK_BASE_PHY_TX);


    //Chip_Clock_DisableBaseClock(CLK_BASE_APB3);
        //Chip_Clock_Disable(CLK_APB3_BUS)
        Chip_Clock_Disable(CLK_APB3_I2C1);
        Chip_Clock_Disable(CLK_APB3_DAC);
        Chip_Clock_Disable(CLK_APB3_ADC0);
        Chip_Clock_Disable(CLK_APB3_ADC1);
        //Chip_Clock_Disable(CLK_APB3_CAN0);
    //Chip_Clock_DisableBaseClock(CLK_BASE_APB1);
        //Chip_Clock_Disable(CLK_APB1_BUS);
        Chip_Clock_Disable(CLK_APB1_MOTOCON);
        //Chip_Clock_Disable(CLK_APB1_I2C0);
        Chip_Clock_Disable(CLK_APB1_I2S);
        Chip_Clock_Disable(CLK_APB1_CAN1);


    Chip_Clock_DisableBaseClock(CLK_BASE_LCD);
    Chip_Clock_DisableBaseClock(CLK_BASE_ADCHS);


    Chip_Clock_DisableBaseClock(CLK_BASE_SDIO);        /*!< Base clock for SDIO */
    Chip_Clock_DisableBaseClock(CLK_BASE_SSP0);        /*!< Base clock for SSP0 */
    Chip_Clock_DisableBaseClock(CLK_BASE_SSP1);        /*!< Base clock for SSP1 */
    Chip_Clock_DisableBaseClock(CLK_BASE_UART0);        /*!< Base clock for UART0 */
    //Chip_Clock_DisableBaseClock(CLK_BASE_UART1);        /*!< Base clock for UART1 */ -> BLE
    Chip_Clock_DisableBaseClock(CLK_BASE_UART2);        /*!< Base clock for UART2 */
    Chip_Clock_DisableBaseClock(CLK_BASE_UART3);        /*!< Base clock for UART3 */
    Chip_Clock_DisableBaseClock(CLK_BASE_OUT);        /*!< Base clock for CLKOUT pin */
    Chip_Clock_DisableBaseClock(CLK_BASE_APLL);        /*!< Base clock for audio PLL */
    Chip_Clock_DisableBaseClock(CLK_BASE_CGU_OUT0);    /*!< Base clock for CGUOUT0 pin */
    Chip_Clock_DisableBaseClock(CLK_BASE_CGU_OUT1);    /*!< Base clock for CGUOUT1 pin */‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

[nxp68994]

Hi team and jeremyzhou,

I want to continue Javier’s question because it was not really answered by jeremyzhou above. In the source packages exist a header “eeprom.h” with the definitions:

uint8_t Chip_EEPROM_Write(uint32_t dstAdd, uint8_t *ptr, uint32_t byteswrt);

uint8_t Chip_EEPROM_Read(uint32_t srcAdd, uint8_t *ptr, uint32_t bytesrd);

This both functions are what I want to have. Unfortunately, the implementation is missing (as Javier pointed out). The file “eeprom_18xx_43xx.c” does not contain these implementation, but similar functions. I checked these function, but it does not work. The EEPROM is clocked and not in POWERDOWN mode, but any write to the EEPROM memory has no effect. I always reading zeros back, before programming the page or after it.

My question to the team is: why the implementation of Chip_EEPROM_Write() cannot be published? Is it protected code?

Also the examples of LPC43xxx/18xxx does not contain a working EEPROM example. What only exists is the file “eeprom_18xx_43xx.c” with some public and private functions.

What I expect if I write to EEPROM memory is that the content is saved and can be read back. I know that the content is persistent saved only after programming. Is this meaning wrong? Where do I find a working example?

Thanks in advance

[javiervallori]

Hi Wolfgang,

I did my own implementation and works. It has not exactly the same interface, but it is quite similar. If you desired I can send it.

[jeremyzhou]

Hi Javier Vallori ,

Thank you for your interest in NXP Semiconductor products and 

for the opportunity to serve you.

You can find some related eeprom functions in the eeprom_18xx_43xx.c and eeprom_18xx_43xx.h.

Have a great day,

TIC

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