Variation in number of cycles for Load/Store in different memory regions?

[himanshudoshi]

Hello to all,

I am considering Load and Store instructions for different memory regions and wanna analyzed their respective effect in the energy-consumption. From my script:

"STR.W R6,[R0]\t\n" 

"STR.W R6,[R0]\t\n"

.

.

.

"STR.W R6,[R0]\t\n" (1000times as interrupt)

and on the basis of the value of R0 register, the number of cycles are varying. For an example: 

SRAMX Memory Location: LDR R0,=#40000002 ;  => Number of cycles:  8

SRAM0 Memory Location: LDR R0,=#20000002 ;  => Number of cycles:  2 

SRAM1 Memory Location: LDR R0,=#20010002 ;  => Number of cycles:  2

SRAM2 Memory Location: LDR R0,=#20020002 ;  => Number of cycles:  2

This is what the result I am getting. And if in the case of accessing the instructions with offset, will show a huge change in the number of cycles up to 12 cycles each instruction. 

Along with that, while trying to access the Flash memory there is no detection of the interrupt. 

Can any body explains me such behavior??. Also, kindly find the attached memory map.

My target board is LPC 54114 and my target processor is ARM Cortex-M4.

Thanking you,

Regards,

Himanshu Doshi

[soledad]

Hi,

The change of the number of cycles from the same instruction when you are trying to get access to different memory areas, it is related, to the architecture of the device, since there is a CortexM4 and CortexM0 , not all the memory  can be access in the same way.   This is reflect in the latency response of the instruction and the one that take the most, it is the one related to the  AHB cross Bar, that need to validate that you have the credetencials to access

For sure this is a expected behavior.

Have a great day,
Soledad

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[himanshudoshi]

Hii Solebad,

First of all thank you very much for your reply. Yes, I understood your point, that accessing different memory regions resultant into latency response of the instruction and it's the major one for the more number of cycles. But, now I have two small issues to mention:

1. As mentioned in my original post, the number of cycles during the memory access SRAMX  is way higher than the others. But, in some documentation, I have read that the cycle count/energy consumption is more when the memory location is far from the flash or in other words, farthest location memory access consume more. And from the architecture, the SRAMX is near to flash, then also why such behavior?

2. Why the relative energy consumption between two instruction varies. For example: If I access sequence of NOP instruction before and after LOAD or STORE instruction. Then, the expected energy consumption should be higher for LOAD/STORE compared with NOP. But, during different memory access, it varies, sometimes it becomes lower than NOP instruction, which is quite unexpected. Can you please tell me why such behavior??

Thank you very much once again,

Regards,

Himanshu