Using LPC4370's HSADC + DMA + EMC SRAM

[diverger]

I need do 80MSPS ADC sampling and store at least 40ms data to external SRAM without missing any data. And finally find LPC4370, the 80MSPS internal ADC is attractive. But I'm not very familiar with LPC's parts, and I have some doubts:

1. Does LPC4370 support DMA from HSADC to external SRAM?
2. Because the big chunk of data, I need at least two SRAM chip, so the address of the DMA destination is not
   continuous, may the 'Scatter or gather DMA' feature of LPC4370's solve this problem?
3. It seems the maximum DMA transfer size is only 4095, so I may split my transfer to multiple DMA xfr? If so, any good suggestions to avoid ADC FIFO overflowing?
4. Can LPC4370 afford such a high bus load? 

Any suggestions are appreciated.

Thanks.

[jeremyzhou]

Hi Hua Zhang,

Thank you for your interest in NXP Semiconductor products and 

the opportunity to serve you.

1. Does LPC4370 support DMA from HSADC to external SRAM?Yes, it does.
2. Because the big chunk of data, I need at least two SRAM chip, so the address of the DMA destination is not
   continuous, may the 'Scatter or gather DMA' feature of LPC4370's solve this problem?

   The Scatter or gather DMA function is capable of handling it.
3. It seems the maximum DMA transfer size is only 4095, so I may split my transfer to multiple DMA xfr? If so, any good suggestions to avoid ADC FIFO overflowing?

       Yes, and I'd like to suggest you reduce the FIFO level to avoid ADC FIFO overflowing in DMA implementation.

   4. Can LPC4370 afford such a high bus load? 

       I think so, and pleae giving a try.
Have a great day,
TIC

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