Using EMC SDRam with diffrent frequency

[friedbertmaier]

We are using a LPC1778FET208 with a SDram IS42SM16800H.

And we have the problem, that the SDram only works with a frequency of the SDram between 18MHz and 38 MHz. It is not possible to use a higher or a lower frequency.

It doesn't matter if we choose the controller frequency or we use the double frequency of the Controller and set EMCCLKSEL=1 to use the half frequency.

In EMCinit we take the timings of the SDram Datasheet. If we take wrong timings (to short or to long) it doesn't work. So we think we have the right values for this timings. And it doesn't mater if we use RAS& CAS = 2 or RAS&CAS =3.

We also tested the Timings with different values in the delay Registers (EMC_CMDDLY and EMC_FBCLKDLY). If we use here high values > 20 then it works with no frequencys.

To take the right mode on the SDram we read the mode with the following funktion: dummy = *((volatile unsigned long *)(0xA0000000 | (3<<0 | 3<<4)<<10). So we have Burst length = 4, CAS Latency =3 and 9 column_bits in the BRC mode.

And we also checked the path length on the pcb borad. Here are no big differences between all the different lines between the controller and the SDram.

So do you have any futher idea what we can check to use this SDram with different frequencies.

[friedbertmaier]

Carsten thank you for your response. I tested it with your configurations, but it doesn't change anything in my testing Report. So I get the same mistakes.

But we tested it also with different frequencies and there are only some frequencies with mistakes. Our SDram is working without any problems when we take the EMC frequencies between 18MHz and 36MHz, 54MHz and over 84MHz. And if we change the Delay Control Registers or the timings of the Dynamic EMC a little bit,  we get the same results. So we think, there are other problems in this initializition.

[jeremyzhou]

Hi Friedbert Maier,

Thank you for your interest in NXP Semiconductor products and 

for the opportunity to serve you.

To provide the fastest possible support, I'd like to refer to the demo for details.

Have a great day,
TIC

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[carstengroen]

Friedbert,

I don't know if this relates to your problem or not (you probably already have seen it) but just wanted to mention it anyway as this exact errata/error has caused me some headache of various kinds when dealing with LPC177x systems....The PCLK divider must only be 1,2,3 or 4. Doing anything higher than 4 will give you some VERY interesting failures of the various peripherals inside the chip. Just as a heads-up

Also, I have a system running with a IS42S16400F (not the same size of chip as you use) my initcode looks like this (EMC running at 60 MHz)

#define SDRAM_PERIOD          16.67  // 72MHz

#define P2C(Period)           (((Period<SDRAM_PERIOD)?0:(uint32_t)((float)Period/SDRAM_PERIOD))+1)

#define SDRAM_REFRESH         7813
#define SDRAM_TRP             20
#define SDRAM_TRAS            45
#define SDRAM_TAPR            1
#define SDRAM_TDAL            3
#define SDRAM_TWR             3
#define SDRAM_TRC             65
#define SDRAM_TRFC            66
#define SDRAM_TXSR            67
#define SDRAM_TRRD            15
#define SDRAM_TMRD            3

/*Set data read delay*/
LPC_SC->EMCDLYCTL |=(8<<8);
LPC_SC->EMCDLYCTL |= (0x08 <<16);
LPC_EMC->Control =1;
LPC_EMC->DynamicReadConfig = 0;
LPC_EMC->DynamicRasCas0 = 0;
LPC_EMC->DynamicRasCas0 |=(3<<8);
LPC_EMC->DynamicRasCas0 |= (3<<0);
LPC_EMC->DynamicRP = P2C(SDRAM_TRP);
LPC_EMC->DynamicRAS = P2C(SDRAM_TRAS);
LPC_EMC->DynamicSREX = P2C(SDRAM_TXSR);
LPC_EMC->DynamicAPR = SDRAM_TAPR;
LPC_EMC->DynamicDAL = SDRAM_TDAL+P2C(SDRAM_TRP);
LPC_EMC->DynamicWR = SDRAM_TWR;
LPC_EMC->DynamicRC = P2C(SDRAM_TRC);
LPC_EMC->DynamicRFC = P2C(SDRAM_TRFC);
LPC_EMC->DynamicXSR = P2C(SDRAM_TXSR);
LPC_EMC->DynamicRRD = P2C(SDRAM_TRRD);
LPC_EMC->DynamicMRD = SDRAM_TMRD;
// 12 row, 8 - col, SDRAM
LPC_EMC->DynamicConfig0 = 0x0000280;‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

I don't know if any of this helps you.

(send me a PM if you need the rest of the SDRAM initcode as there is quite some more to it!)