USB Host mode Host init error 3 LPC54605J256

[SOOTY1]

Hi friends,

I'm having a problem trying to init the usb host.  No matter what I try, it keeps giving error 3 - can't locate driver instance?  Any insight welcome.  thank you.

LPC54605J256.  Custom board.

I have some parts of the usb seemingly operational -
here's the main, and prints of the usb system.

I am a newcomer to embedded so I have probably overlooked something, perhaps in the usb numbering, or the extra usb init in main.  I have tried to only use the config tools. 

Clocks, pins and peripherals are all looking good, relevant usb pins, host mode, nvic, enabled.  fsl-power.h is included.  USB is taking PLL at 48Mhz.  I have the correct resistor REXT value.  All config tools defined USB pins and USBHSH are defined as demanded by tool.

USBID is, not tied in any direction, but that can be forced with portmode as I understood it? 

Power is provided to the keypad.  VUSB - 4.5v.  LED lights on the keypad, but as init fails, nothing more happens : )

I have checked the controller ID.  I'm using for High Speed Host.
#define CONTROLLER_ID kUSB_ControllerIp3516Hs0
it is declared in host config.h as 1U

int main(void)
{
vPortDefineHeapRegions(xHeapRegions);

BOARD_InitBootPins();
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();

SEGGER_RTT_Init();

PRINTF("System Booting...\r\n");

/* USB1 HS PHY POWER */
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);

/* ENABLE USB1 HS HOST CLOCK */
CLOCK_EnableClock(kCLOCK_Usbh1);
CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);

/* FORCE USB1 INTO HOST MODE */
USBHSH->PORTMODE &= ~(1UL << 16);
USBHSH->PORTMODE |= (1UL << 16);

/* Small delay for PHY */
for (volatile uint32_t d = 0; d < 180000; d++) __NOP();

PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE);
PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1);
PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS);
PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD);

/* START USB HOST STACK */
usb_status_t usbStatus = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent);

if (usbStatus == kStatus_USB_Success)
{
PRINTF("USB HOST INIT OK\r\n");
}
else
{
PRINTF("USB HOST INIT FAILED: %d\r\n", (int)usbStatus);
}

Process: JLinkGDBServerCLExe
System Booting...
USB PORTMODE = 0x00050000
USBHSH->PORTSC1 = 0x00001000
USBHSH->USBSTS = 0x00000000
USBHSH->USBCMD = 0x00000501
USB HOST INIT FAILED: 3
Starting scheduler...

[SOOTY1]

@carlos_o  hi, just to show the register value is not changing even after setting with config tools and visible in clockconfig.c generated file -

System Booting...
Core clock = 96000000 Hz
After BOARD_InitBootClocks:
USB PLL freq = 0 Hz
Clock enable returned: 1
USB PLL freq = 0 Hz
USB1CLK freq = 0 Hz
USB PORTMODE = 0x00050000
USBHSH->PORTSC1 = 0x00001000
USBHSH->USBSTS = 0x00000000
USBHSH->USBCMD = 0x00000501

--- USB CLOCK DIAGNOSTICS ---
USBPLLCTRL : 0x00000D3F
USBPLLSTAT : 0x00000001
USB1CLKSEL : 0x00000002
USB1CLKDIV : 0x00000000
PDRUNCFG : 0x40000610
--- END USB CLOCK DIAGNOSTICS ---

USB_HostInit failed with status 3

look we can see that, even though the clockconfig.c states USB1CLK is set to MAINCLKSELA -

it is not actually changing the register value - 

void BOARD_BootClockRUN(void)
{
/*!< Set up the clock sources */
/*!< Set up FRO */
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
being below the voltage for current speed */
POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) | SYSCON_SYSOSCCTRL_FREQRANGE(1U)); /*!< Set system oscillator range */
/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
before calling this API since this API is implemented in ROM code */
CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */

/*!< Set up SYS PLL */
const pll_setup_t pllSetup = {
.pllctrl = SYSCON_SYSPLLCTRL_SELI(16U) | SYSCON_SYSPLLCTRL_SELP(8U) | SYSCON_SYSPLLCTRL_SELR(0U),
.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
.pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
.pllRate = 180000000U,
.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
};
CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source*/
CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
/*!< Set up AUDIO PLL */
const pll_setup_t audio_pllSetup = {
.pllctrl = SYSCON_AUDPLLCTRL_SELI(59U) | SYSCON_AUDPLLCTRL_SELP(31U) | SYSCON_AUDPLLCTRL_SELR(0U),
.pllmdec = (SYSCON_AUDPLLMDEC_MDEC(30583U)),
.pllndec = (SYSCON_AUDPLLNDEC_NDEC(1U)),
.pllpdec = (SYSCON_AUDPLLPDEC_PDEC(5U)),
.pllRate = 48000000U,
.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
};
CLOCK_AttachClk(kEXT_CLK_to_AUDIO_PLL); /*!< Set audio pll clock source*/
CLOCK_SetAudioPLLFreq(&audio_pllSetup); /*!< Configure PLL to the desired value */

/*!< Set up USB PLL */
const usb_pll_setup_t usb_pllSetup = {
.msel = 95U,
.nsel = 3U,
.psel = 0U,
.direct = true,
.bypass = false,
.fbsel = false,
.inputRate = 12000000U,
};
CLOCK_SetUsbPLLFreq(&usb_pllSetup); /*!< Configure PLL to the desired value */

/*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
before calling this API since this API is implemented in ROM code */
CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */

/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true); /*!< Reset USB0CLKDIV divider counter and halt it */
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 6U, false); /*!< Set USB0CLKDIV divider to value 6 */
CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 0U, true); /*!< Reset USB1CLKDIV divider counter and halt it */
CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2U, false); /*!< Set USB1CLKDIV divider to value 2 */
CLOCK_SetClkDiv(kCLOCK_DivSctClk, 0U, true); /*!< Reset SCTCLKDIV divider counter and halt it */
CLOCK_SetClkDiv(kCLOCK_DivSctClk, 48U, false); /*!< Set SCTCLKDIV divider to value 48 */

/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; /*!< Enable ASYNC APB subsystem */
CLOCK_AttachClk(kMAIN_CLK_to_ASYNC_APB); /*!< Switch ASYNC_APB to MAIN_CLK */
CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); /*!< Switch USB0_CLK to USB_PLL */
CLOCK_AttachClk(kFRO_HF_to_USB1_CLK); /*!< Switch USB1_CLK to MAIN_CLK */
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM2); /*!< Switch FLEXCOMM2 to AUDIO_PLL */
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to AUDIO_PLL */
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM5); /*!< Switch FLEXCOMM5 to AUDIO_PLL */
CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM7); /*!< Switch FLEXCOMM7 to AUDIO_PLL */
CLOCK_AttachClk(kAUDIO_PLL_to_SCT_CLK); /*!< Switch SCT_CLK to AUDIO_PLL */
/*!< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

(from main shown here)
int main(void)
{
vPortDefineHeapRegions(xHeapRegions);

BOARD_InitBootPins();
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();

SEGGER_RTT_Init();

PRINTF("System Booting...\r\n");
PRINTF("Core clock = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_CoreSysClk));
PRINTF("After BOARD_InitBootClocks:\n");
PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));

/* === Recommended Power-up Order === */
POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); // Crystal analog domain - FIRST
POWER_DisablePD(kPDRUNCFG_PD_VD3); // PLL domain
POWER_DisablePD(kPDRUNCFG_PD_VD5); // PHY domain
POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);


SDK_DelayAtLeastUs(15000, SystemCoreClock); // 15ms — give crystal time to stabilize

/* Force crystal oscillator */
SYSCON->SYSOSCCTRL = 0x00000000;

// CLOCK_EnableClock(kCLOCK_Usbh1);

status_t clkStatus = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);
PRINTF("Clock enable returned: %d\r\n", clkStatus);

PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));
PRINTF("USB1CLK freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbClk));

/* Force Host mode - bit 16 */
USBHSH->PORTMODE &= ~(1UL << 16);
USBHSH->PORTMODE |= (1UL << 16);

PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE);
PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1);
PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS);
PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD);
PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n");

/* USB PLL state */
PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL);
PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT);

/* USB1 clock mux + divider */
PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL);
PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV);

/* Power gating snapshot */
PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG);


/* Optional SDK-level view (if available) */
// PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));

PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n");

/* Init stack */
usb_status_t status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent);
if (status != kStatus_USB_Success) {
PRINTF("USB_HostInit failed with status %d\r\n", status);
}

[SOOTY1]

I tried some more and it seems USB clock is failing to attach properly and run.  It is selected correctly in clock config with 48Mhz input, from USBPLL.

int main(void)
{
vPortDefineHeapRegions(xHeapRegions);

BOARD_InitBootPins();
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();

SEGGER_RTT_Init();

PRINTF("System Booting...\r\n");
PRINTF("Core clock = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_CoreSysClk));

/* Power and Clock */
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);
POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); // External crystal analog domain
POWER_DisablePD(kPDRUNCFG_PD_VD3); // USB PLL domain
POWER_DisablePD(kPDRUNCFG_PD_VD5); // USB PHY domain
SDK_DelayAtLeastUs(1500, SystemCoreClock);
CLOCK_EnableClock(kCLOCK_Usbh1);
CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);  [I don't know should it be 48M or 480M here neither work anyway]

PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));
PRINTF("USB1CLK freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbClk));
/* Force Host mode - bit 16 */
USBHSH->PORTMODE &= ~(1UL << 16);
USBHSH->PORTMODE |= (1UL << 16);

PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE);
PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1);
PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS);
PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD);
PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n");

/* USB PLL state */
PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL);
PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT);

/* USB1 clock mux + divider */
PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL);
PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV);

/* Power gating snapshot */
PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG);

/* Optional SDK-level view (if available) */
// PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));

PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n");

/* Init stack */
usb_status_t status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent);
if (status != kStatus_USB_Success) {
PRINTF("USB_HostInit failed with status %d)\r\n", status);
}

gives - 

Process: JLinkGDBServerCLExe
System Booting...
Core clock = 180000000 Hz
USB PLL freq = 0 Hz
USB1CLK freq = 0 Hz
USB PORTMODE = 0x00050000
USBHSH->PORTSC1 = 0x00001000
USBHSH->USBSTS = 0x00000000
USBHSH->USBCMD = 0x00000501

--- USB CLOCK DIAGNOSTICS ---
USBPLLCTRL : 0x00000D3F
USBPLLSTAT : 0x00000001
USB1CLKSEL : 0x00000002
USB1CLKDIV : 0x00000000
PDRUNCFG : 0x40000610
--- END USB CLOCK DIAGNOSTICS ---

USB_HostInit failed with status 3)

Is it something in the powerup sequence is incorrect?  I really don't know now.
I have tried so long on this.  I think the incorrect driver/not found is also a separate thing.
I have even less of an idea with that - I have it registered in the .map, enabled in the host_config, included in the build, present in the workspace . .

[SOOTY1]

I put in some more print statements to look at the clock.  It's set up right in clocks tool, but seems not to be running normally?

/* ====================== MAIN ====================== */
int main(void)
{
vPortDefineHeapRegions(xHeapRegions);

BOARD_InitBootPins();
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();

SEGGER_RTT_Init();

PRINTF("System Booting...\r\n");

/* USB1 HS PHY POWER */
// POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);

/* ENABLE USB1 HS HOST CLOCK */
// CLOCK_EnableClock(kCLOCK_Usbh1);

// CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);
// status_t status;

// status = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 480000000U);

// PRINTF("USB host clock init status = %d\r\n", status);

/* FORCE USB1 INTO HOST MODE */
USBHSH->PORTMODE &= ~(1UL << 16);
USBHSH->PORTMODE |= (1UL << 16);

/* Small delay for PHY */
for (volatile uint32_t d = 0; d < 180000; d++) __NOP();

PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE);
PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1);
PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS);
PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD);
PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n");

/* USB PLL state */
PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL);
PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT);

/* USB1 clock mux + divider */
PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL);
PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV);

/* Power gating snapshot */
PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG);

/* SDK-level view */
PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbClk));

PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n");

/* START USB HOST STACK */
usb_status_t usbStatus = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent);

if (usbStatus == kStatus_USB_Success)
{
PRINTF("USB HOST INIT OK\r\n");
}
else
{
PRINTF("USB HOST INIT FAILED: %d\r\n", (int)usbStatus);
}

System Booting...
USB PORTMODE = 0x00050000
USBHSH->PORTSC1 = 0x00001000
USBHSH->USBSTS = 0x00000000
USBHSH->USBCMD = 0x00000501

--- USB CLOCK DIAGNOSTICS ---
USBPLLCTRL : 0x00001017
USBPLLSTAT : 0x00000001
USB1CLKSEL : 0x00000002
USB1CLKDIV : 0x00000005
PDRUNCFG : 0x40000610
USB1CLK freq: 0
--- END USB CLOCK DIAGNOSTICS ---

[SOOTY1]

@carlos_o 

I'm still having the problems with the SDK (see thread for more details)

I have today changed SDK to 25.06.00 and updated the Config Tools to 26.03 also

I still get the USB Host init fail error code 3.  PLL is not starting, even though it seems configured by the book in the config tools clock tree.  

Any insight is very welcome.
thanks,

[carlos_o]

Hi @SOOTY1 

Apologize the late reply and thank you for the detailed testing you have done.

Could you please remove the call to

CLOCK_EnableClock(kCLOCK_Usbh1);

before calling

CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);

The reason is that the clock enable is already handled inside CLOCK_EnableUsbhs0HostClock(). Additionally, some peripherals must be disabled before changing their configuration, and enabling the clock beforehand may prevent proper reconfiguration.

Let me know your results. 

[SOOTY1]

@carlos_o hi, no worries, thanks for getting back to me!

Ok I removed the clock call as suggested.   It is still failing though.
What's strange is that it reports the USB1CLKDIV as 0x0 every time. (its div by 6 derived from 288Mhz USBPLL) but maybe that's because its not running PLL yet?  Even without any of this power up sequence it wasn't starting up PLL.  I do have a 12Mz xtal on the board. 

I also tried to change the settings away from USBPLL, to MAINCLKSELA - with 96Mhz divided down to feed USB1CLK, but although I could see Core clock Freq. change to 96Mhz, USBCLKDIV remained 0x0 (selected was /2) and USBCLKSEL 0x00000002. (should have changed value to reflect MAINCLKSELA)
I don't know what to make of that.

System Booting...
Core clock = 180000000 Hz
After BOARD_InitBootClocks:
USB PLL freq = 0 Hz
Clock enable returned: 1
USB PLL freq = 0 Hz
USB1CLK freq = 0 Hz
USB PORTMODE = 0x00050000
USBHSH->PORTSC1 = 0x00001000
USBHSH->USBSTS = 0x00000000
USBHSH->USBCMD = 0x00000501

--- USB CLOCK DIAGNOSTICS ---
USBPLLCTRL : 0x00000D3F
USBPLLSTAT : 0x00000001
USB1CLKSEL : 0x00000002
USB1CLKDIV : 0x00000000
PDRUNCFG : 0x40000610
--- END USB CLOCK DIAGNOSTICS ---

USB_HostInit failed with status 3

current main is 

int main(void)
{
vPortDefineHeapRegions(xHeapRegions);

BOARD_InitBootPins();
BOARD_InitBootClocks();
BOARD_InitBootPeripherals();

SEGGER_RTT_Init();

PRINTF("System Booting...\r\n");
PRINTF("Core clock = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_CoreSysClk));
PRINTF("After BOARD_InitBootClocks:\n");
PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));

/* === Recommended Power-up Order === */
POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); // Crystal analog domain - FIRST
POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC);
POWER_DisablePD(kPDRUNCFG_PD_VD3); // PLL domain
POWER_DisablePD(kPDRUNCFG_PD_VD5); // PHY domain
POWER_DisablePD(kPDRUNCFG_PD_USB_PLL);
POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY);

SDK_DelayAtLeastUs(15000, SystemCoreClock); // 15ms — give crystal time to stabilize

/* Force crystal oscillator */
SYSCON->SYSOSCCTRL = 0x00000000;

// CLOCK_EnableClock(kCLOCK_Usbh1);

status_t clkStatus = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);
PRINTF("Clock enable returned: %d\r\n", clkStatus);

PRINTF("USB PLL freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));
PRINTF("USB1CLK freq = %lu Hz\r\n", CLOCK_GetFreq(kCLOCK_UsbClk));

/* Force Host mode - bit 16 */
USBHSH->PORTMODE &= ~(1UL << 16);
USBHSH->PORTMODE |= (1UL << 16);

PRINTF("USB PORTMODE = 0x%08lX\r\n", USBHSH->PORTMODE);
PRINTF("USBHSH->PORTSC1 = 0x%08lX\r\n", USBHSH->PORTSC1);
PRINTF("USBHSH->USBSTS = 0x%08lX\r\n", USBHSH->USBSTS);
PRINTF("USBHSH->USBCMD = 0x%08lX\r\n", USBHSH->USBCMD);
PRINTF("\r\n--- USB CLOCK DIAGNOSTICS ---\r\n");

/* USB PLL state */
PRINTF("USBPLLCTRL : 0x%08lX\r\n", SYSCON->USBPLLCTRL);
PRINTF("USBPLLSTAT : 0x%08lX\r\n", SYSCON->USBPLLSTAT);

/* USB1 clock mux + divider */
PRINTF("USB1CLKSEL : 0x%08lX\r\n", SYSCON->USB1CLKSEL);
PRINTF("USB1CLKDIV : 0x%08lX\r\n", SYSCON->USB1CLKDIV);

/* Power gating snapshot */
PRINTF("PDRUNCFG : 0x%08lX\r\n", SYSCON->PDRUNCFG);

/* Optional SDK-level view (if available) */
// PRINTF("USB1CLK freq: %lu\r\n", CLOCK_GetFreq(kCLOCK_UsbPll));

PRINTF("--- END USB CLOCK DIAGNOSTICS ---\r\n\r\n");

/* Init stack */
usb_status_t status = USB_HostInit(CONTROLLER_ID, &g_HostHandle, USB_HostEvent);
if (status != kStatus_USB_Success) {
PRINTF("USB_HostInit failed with status %d\r\n", status);
}

[carlos_o]

Hi @SOOTY1,

Thanks for your post!

Could please share which SDK version you are using?

Please review the return value of CLOCK_EnableUsbhs0HostClock.

You could refer to the USB Host examples at the SDK for the LPCXpresso54608 board but that examples use USB FS instead of HS. 

To have high-speed USB operating, the CPU clock must be configured to a
minimum frequency of 60 MHz.

BR.

[SOOTY1]

Hi Carlos, thanks for your quick reply. 

I'm using SDK 2.14.0 (I tried to use more modern, but it failed on a, I believe also a USB driver actually - IDE stated mismatch between SDK (latest) and needed (older) driver) Sorry I don't remember the details of that now.

I'm using a CPU system clock of 180Mhz. 

with this - 

CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);
status_t status;

status = CLOCK_EnableUsbhs0HostClock(kCLOCK_UsbSrcUsbPll, 48000000U);

PRINTF("USB host clock init status = %d\r\n", status);

I return -
USB host clock init status = 1

does that help?