USB HS PLL not Locking on LPC55S69

[martinjaymckee]

I am working on my first USB enabled product with an LPC series microcontroller, and it is the first time that I have worked with the PHY directly. This is on a custom board, using the USB1 high-speed USB connection.

I am currently trying to get the dev_cdc_vcom_bm SDK example working on my device (after testing it on the LPCXpresso55S69 dev board). The obvious difference on my custom board is that it has a 20MHz crystal mounted rather than 16MHz. 

I have tracked down, as my first problem, that the PLL_SIC register is showing PLL_LOCK as 0, so the PLL is not locking. USB clock, USB PLL power, and USB PLL enable are enabled. The clock divisor is set for divide by 24 (value4) for the 20MHz clock. PLL_PREDIV = 0. USB1_3V3 is reading a solid 3.299v, so the input voltage seems fine.

One other potential issue is that I'm using a 20MHz oscillator and not a 20MHz crystal. I saw another thread where that was the issue, but it was on a Kinetis part, and I'm not sure it's the same IP. Even if it is, I wouldn't be surprised if that was a red herring.

Attached is the schematic of the device, though that shouldn't be the issue in this case.

Any thoughts about where to look next as far as getting the PLL to lock? 

[Harry_Zhang]

Hi @martinjaymckee 

Looking at your schematic, the LPC55S69 XTAL32M_P pin is driven from an ECS-2520MVLC-200-CN oscillator output, while XTAL32M_N is left unconnected.

The USB HS PLL on LPC55S69 derives its reference from the system oscillator block. The SDK examples typically assume a crystal connected between XTAL32M_P and XTAL32M_N.

When using an external clock source instead of a crystal, the oscillator block should be configured differently.

BR

Harry

[martinjaymckee]

Okay, that's fair. I do have XO32M configured to use use the buffer bypass. And I have verified that the main clock PLL is using the correct oscillator input.

Are there other configurations that I need too change on the XO32M clock block to make the USB PLL work?