Tips for dual core performance on LPC55S69?

[scottm]

I thought I saw an app note on optimizing dual-core performance on the LPC55S6x family, but I can't find anything now.

Does such a resource exist? What I'm mostly looking for is information on memory contention. I see that both cores share the same flash memory interface. What kind of performance is achievable with both cores running from flash? Does the second core need to be running from RAM to be useful?

Thanks!

[ZhangJennie]

Hi scottm 

For LPC55 dual core communication, I suggest you referring "LPC55xx/LPC55Sxx Dual Core Communication"

https://www.nxp.com.cn/docs/en/application-note/AN12335.pdf

and "LPC55xx/LPC55Sxx Dual-Core Debug in MCUXpresso"

https://www.nxp.com.cn/docs/en/application-note/AN12358.pdf

Hope this helps,

Jun Zhang

[scottm]

Hi Jun,

I've read those, and AN12335 does mention running code from an alternate RAM bank for best performance.

What I'm looking for is more information on how to structure things when it's not feasible to run the whole thing from RAM, and what kind of performance hit I can expect. I don't see anything at all in NXP's docs about running both cores from flash, but I'm sure I've seen information somewhere about using both cores with FreeRTOS and I don't think that involved completely separate copies of the RTOS.

This seems like a big topic that ought to have a lot of discussion somewhere. If it's not in NXP's documentation, is there ARM documentation I should be reading instead?

Thanks,

Scott

[ZhangJennie]

HI scottm 

I don't think this is a NXP documentation.

Thanks,

Jun Zhang