Timing of DMA descriptor reload on LPC 54102.

[chrisoneill]

I have a sequence of DMA descriptors for a SPI slave for a single SPI operation.  The incoming command can be either a read or write, so based in the command the 'later' data descriptors are configured as to data source (read), data destination (write), and count.

What is the timing of the reload of transmit descriptors?  If I have an intermediate 'turn-around' descriptor to allow for configuration of the read or write descriptors, what is the time limit?  For transmit, at what point during the execution of the 'turn-around' descriptor is the next (data transmit) descriptor loaded?  Is there buffering in the transmitter?  For a 2-byte turn-around, how much time do I have to configure the data transmit descriptor before it gets loaded?  The full 2-byte transmit time, or less?

A timing diagram for SPI slave DMA descriptor loading would be a big help. 

[Alexis_A]

Dear Chris, 

To avoid any kind of issues between the descriptors reload timing, I will suggest to link the descriptors between them, check the following link to know how to do this:

https://community.nxp.com/docs/DOC-334851 

Best Regards,

Alexis Andalon

[chrisoneill]

Hi Alexis

I am using linked descriptors.  One difference is that I'm configuring the descriptor for the data read or write based on the information in the first descriptor.  If it's a read command, I have to set the .source pointer in the Tx descriptor.  If it's a write command, I have to set the .dest pointer in the Rx descriptor.  This happens while a 'turn-around' Rx descriptor is being executed.  My question is that for a read command, while the 'turn-around' Rx descriptor is being executed, at what point in time does it become invalid to configure the .source pointer and xfercfg length in the Tx data descriptor?  It doesn't seem like I have the entire 2-byte time of the 'turn-around' descriptor, which I would expect, in that there would be some non-zero cycle time to load it.

Processor at 96 MHz.  Two bytes = 16 bits, 20 MHz SPI clock, I should have around 5 CPU cycles per bit, = 80 cycles.

Interrupt latency = 16 cycles, DMA irq is around 40 cycles, 56 is less than 80.  Should work, unless the DMA engine reload mechanism is reading the next descriptor before the current one is exhausted.  That's the timing I need to know.

How many cycles before the next descriptor is executed does the DMA engine actually read it?

My use case is:

Rx descriptors:      4-byte      2-byte      N bytes

Tx descriptors:      6-byte -------------      N bytes

Interrupt triggered at end of first Rx descriptor, 4 bytes.  While 2-byte Rx descriptor and last 2 bytes of first Tx descriptor are executing, configure the third Rx descriptor and second Tx descriptor.

One more question:  What is the purpose of the initial descriptor if it's configured identical to the first descriptor?  Can't the first descriptor in the sequence be used as the initial descriptor?

In my case I re-use the 3 Rx descriptors and 2 Tx descriptors for processing each SPI DMA operation, where the first Rx and first Tx descriptors are the initial descriptors, and reloaded by the third Rx descriptor and second Tx descriptor, respectively.

One more question: My implementation works for multi-byte exchanges, but not a single byte read or write.  Does the descriptor mechanism support single byte reads and writes?

[Alexis_A]

Hello Chris

One more question:  What is the purpose of the initial descriptor if it's configured identical to the first descriptor?  Can't the first descriptor in the sequence be used as the initial descriptor?

I think the first descriptor is to trigger the transfer, with the correct managment I think you could use 

One more question: My implementation works for multi-byte exchanges, but not a single byte read or write.  Does the descriptor mechanism support single byte reads and writes?

Yes, this will depend of the transfer size of the DMA channel.

In my sugestion, syncronize the DMA in base of the time could be a little tricky and not reliable in my opinion, it will be better for example, use the SPI IRQ to know where the descriptor needs to change. The DMA interruption will not trigger until the FIFO is full so you have the time between each byte to reload the descriptor.

Best Regards,

Alexis Andalon