1 In fine correction method,
ENET 1588 timer should run under 50MHz CLK, thus 50MHz*43ns = 0x7fff fff made the nanosecond register reach to 0x7fff fff every second , but this CLK may drift to other frequency so we have to adjust addend register to adjust the frequency ,under which 43ns was add to system timer, if the frequency drift to 66MHz so we make addend register to 2^32/1.32 , thus 43ns was added to nanosecond every 1.32 66MHz clk , make result as under 50MHz CLK, is my understanding right?
2 On page 864 of manual, described ref clk drifted to 65MHz,66MHz,67MHz, what if the ref CLK drift to 45MHz, then 45/50=0.9, addend value should = 2^32/0.9? but this overflows,
here is my test data time offset between slave and master:slaveSyncTime - masterSyncTime
if offset<0 means , slave needs to run faster, we have to make addend register value bigger, what if addend register value is already 0xffff ffff?
3 I use the addend value adjustment algorithm on page 865,but slave clk offset to master clk hop, the offset may be -200ms, 125us,11ms. -28ms 140us.. ... offser not stable, slave clk not locked to master
bellow is my way, please correct me
FreqCompensationValue_0 = 0xffff ffff
MasterClockTime_n_1: timestamp got in last followUp msg
MasterClockTime_n: timestamp got in current followUp msg
SlaveClockTimen_n_1 :timestamp got when last sync msg arrived
SlaveClockTimen_n :timestamp got when current sync msg arrive
MasterClockCount_n = MasterClockTime_n - MasterClockTime_n_1 (MasterClockCount_n int32 with unit of nanosecond)
SlaveClockCount_n = SlaveClockTimen_n - SlaveClockTime_n_1 (SlaveClockCount_n int32 with unit of nanosecond)
FreqScaleFactor_n= (MasterClockCount_n + MasterClockCount_n - SlaveClockCount_n )*1.0/SlaveClockCount_n
FreqCompensationValue_n = FreqScaleFactor_n * FreqCompensationValue_n_1
I set FreqCompensationValue_0 = 0xffff ffff, but I found that if FreqScaleFactor_n >1(slave needs to run faster?) and FreqCompensationValue_n_1 = 0xffff ffff, take FreqScaleFactor_n = 1.045412 for example,
FreqCompensationValue_1 = 1.045412* FreqCompensationValue_0 = 1.045412*0xffff ffff = 0xffff ffff,
that means addend register is not adjusted.
where is the wrong understanding?
Your understandings are correct and you are doing exactly the way it is supposed to be done, but if you are having a drift in the clock of so much not keeping the drift in +- 1MHZ then, the issue it is your HW clock that provides the signal, this should be stable enough to maintain the device working fine.
Even without 1588 this would be an issue, for the Ethernet protocol, like the auto-negotiation, etc.
Have a nice day,
Have you tried to use the API in the SDK for the LPC546xx.
For the 1588_Enet Example there is a function utilized inside that corrects the timer, both adding or subtracting, whatever is necessary.
This function uses the coarse method, which essentially tries to correct it in one cycle, but due to a variety of factors it can take several clock cycles to correct. The function is called ENET_Ptp1588CorrectTimerInCoarse.
The description you have stated in your above posts are to implement the coarse method. It is not actually changing the frequency of the clock. Instead you are calculating and offset value to sync the time, which is added or subtracted from the system time.
In other words, the master clock periodically sends a Sync message based on its local clock to a slave clock. It marks the exact time the Sync message is sent, and a Follow_Up message with the exact time information is immediately sent to the slave clock. The slave clock time stamps the arrival of the Sync message, compares the arrival time to the departure time provided in the Follow_Up and is then able to identify the amount of latency in the operating system and adjust its clock accordingly.
Let me know if this helps.
thanks for helping.
ENET_Ptp1588CorrectTimerInCoarse may cause system time jitters.
So I want to use ENET_Ptp1588CorrectTimerInFine to adjust system time smoothly.