Hi,
we are using the AOI0 to trigger the DMA0 and move the contents of the ADC1 ResultFIFO1 to a RAM buffer.
This works fine and allows us to do some oversampling of 2 ADC inputs and average the signals.
Now we would like to extend this oversampling with an additional ADC input which is sampled to ADC1 ResultFIFO0.
I have defined a new DMA channel for the new DMA request "ADC1 FIFO 0" where the source start address is set to &(ADC1->RESFIFO[0]) and the destination address to my new buffer in RAM.
The original DMA channel has received priority 2, while the new channel has been assigned priority 4.
The new DMA request is triggered by the same signal (AOI0_OUT0) as the original DMA request, but when executing this configuration on the hardware, this gives some unexpected results on both the original and the new samples when I check the contents of the RAM-buffers with Freemaster.
The values from "ADC1 FIFO 1" transferred by the original DMA channel seem to be switched every once in a while, so that the value from "sample A" appears in the RAM-buffer where the value for "sample B" should be located and vice versa.
In between these "glitches", the sampled values look OK for anything between 1 and 50 samples.
An explanation could be a missing trigger of the DMA, where a sample will be missing and therefor the contents of the RAM-buffer are not aligned properly.
- Can this be caused by using the same triggger signal (AOI0_OUT0) for the two DMA requests?
- Shouldn't the DMA channel priority guard against this interference?
- Is there another way to configure the LPC to what we would like to achieve?
Kind regards,
Jörn
