Some errors/remarks in/for User Manual LPC800 Rev. 1.1 - 24 January 2013, Request for AppNote, ErrataSheet available?

lpcware · ‎06-15-2016

Content originally posted in LPCWare by capiman on Sat Mar 09 03:18:44 MST 2013
Here are again some topics for user manual of LPC800 (based on rev. 1.1 - 24 January 2013):

1) There are 4 places on page 43 which mention GPREG4. But in table 42 on page 43, the GPREGx goes only from 0 to 3.

2) Registers from Cortex-M0+ itself (e.g. SCB registers like SCR, but also NVIC register like ISER or ICER)
are not described in user manual of LPC800. Would it be possible to describe all registers
which are available in LPC800? Otherwise one must look into different sources (e.g. ARM website to collect the information needed)...
And there is still the unsecurity that register / functionality / certain bits are perhaps not even implemented in LPC800,
because they are optional.

3) Device ID register returns values which are not equal to values mentioned in user manual:
In real device i get:
LPC_SYSCON->DEVICE_ID=1812202B
In user manual the following values are listed:
(http://docs.lpcware.com/lpc800um/RegisterMaps/syscon/r-DeviceIDregister.html#d1e5037__CHDFFBBD)
0x0000 8100 = LPC810M021FN8
0x0000 8110 = LPC811M001FDH16
0x0000 8120 = LPC812M101FDH16
0x0000 8121 = LPC812M101FD20
0x0000 8122 = LPC812M101FDH20 (via ISP i get value 0x00008122)

There is a "8122" in above number, perhaps only 16 bit and bit range wrong?

BTW: My LPC812 chip has bootloader version 13.1 (according to FlashMagic)

4) I would be happy if there is an AppNote for Deep Power Down mode for the Cortex-M0+ LPC800...

5) Is there already an ErrataSheet for the LPC800? I have not found one...

6) I am currently trying to use Deep Power Down mode and wake up via WKT.
This works once, but not a second time. Is there something known not to be working or needed a workaround?
I write a separate entry, with more details inside.

lpcware · ‎06-15-2016

Content originally posted in LPCWare by peterhull90 on Fri Jun 21 06:17:59 MST 2013
(duplicate)

lpcware · ‎06-15-2016

Content originally posted in LPCWare by peterhull90 on Fri Jun 21 06:17:10 MST 2013

(duplicate)

lpcware · ‎06-15-2016

Content originally posted in LPCWare by peterhull90 on Fri Jun 21 06:14:32 MST 2013

Section 21.6.1 Memory map after any reset says '...The RAM usage is described later in this chapter...' but as far as I can see it is not.

Peter

lpcware · ‎06-15-2016

Content originally posted in LPCWare by kimmoli on Fri Jun 21 03:19:10 MST 2013

Ok, my bad.

The struct itself is according to the document.

<code>typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t CTRL;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR; /* 0x10 */
.....
</code>

lpcware · ‎06-15-2016

Content originally posted in LPCWare by noahk on Thu Jun 20 17:46:00 MST 2013

Hi Kimmo,

Looks like you are mistaking alphabetical ordering for register ordering. The tool you are using is listing the registers alphabetically and the order in the document is address order.

Noah

lpcware · ‎06-15-2016

Content originally posted in LPCWare by kimmoli on Thu Jun 20 03:13:19 MST 2013

Following things also are strangely in UM10601 rev 1.2

ADDRDET description in table 161. I would keep descriptions, just swap "Enabled" and "Disabled".

Second is register address offsets for INTENSET and INTENCLR -registers in table 159

The registers INTENSET and INTENCLR are defined in struct in different order, and they work as expected. How ever in manual seems that they are in wrong place.

Maybe this will be useful for someone

-kimmo

lpcware · ‎06-15-2016

Content originally posted in LPCWare by NXP_Paul on Mon Apr 08 08:54:53 MST 2013

Mike
Thanks again for bringing this to our attention. I have made a note of the problem, and it should hopefully be fixed in the next revision of the user's manual.

Paul

lpcware · ‎06-15-2016

Content originally posted in LPCWare by TheShed on Wed Mar 27 14:24:01 MST 2013
Rev 1.2 User Manual available:

http://www.nxp.com/documents/user_manual/UM10601.pdf

and an Errata sheet:

http://www.nxp.com/documents/errata_sheet/ES_LPC81XM.pdf

-----------------------------------------------------------
Errors in Rev 1.2:

1) Fig 37: SPI Transfer_delay timing is a copy of Fig 36: Frame_delay timing.

--
mike

lpcware · ‎06-15-2016

Content originally posted in LPCWare by NXP_Paul on Wed Mar 13 11:22:48 MST 2013
Thank you for bringing these issues to our attention.
1. There are actually five GPREG registers. This will be shown in the next revision of User Manual UM10601.
2. Some of these registers will be included in the next revision of UM10601. The registers in the NVIC will probably not be included in the next version, but they will be incorporated in future revisions.
3. The DEVICE_ID register address in the UM10601 v1.1 is incorrect. It should be 0x400483F8. Again, you will find this value updated in the User Manual that should be available very soon.
4. At this time, we don't have an app note discussing deep power-down. However, we do have example code available for download at http://www.lpcware.com/gfiles/devper/lpc800, that includes wake from deep power-down.
5. An errata sheet for the LPC8xx should be posted to lpcware.com very soon.
6. Please review the example code, and let us know if you are still experiencing problem.