Setting up I2S with PLLAUDIO clock

[lpcware]

Content originally posted in LPCWare by cjutzi on Thu Sep 19 15:59:38 MST 2013
we'd like to drive audio with the PLLAUDIO clock however I don't see anywhere in the sample code where this is setup and used.. It appears the sample uses

Rev. 2.2 — 25 January 2013 User manual has figures on page 1038.. shows the plumbing, but is not configured.. It appears to be using PCLK ..

is there some sample code that sets this up such that the PLLAUDIO is the primary driver of the I2S?

thx
Curt

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Sep 24 05:36:15 MST 2013
The diagrams in the I2S chapter show PLLAUDIO as input into the MCLK path. The naming PLLAUDIO in the figures is misleading. It implies that it is the output frequency of the audio PLL. In fact it is the frequency BASE_APLL_CLK --> PLLAUDIO = BASE_APLL_CLK. And by default BASE_APLL_CLK is set to IRC (= 12 MHz).
I think this is what you see, it is really the PCLK.

You need to connect BASE_APLL_CLK to the output of the Audio PLL (in register 0x400500C0), then you will see this frequency on the TX_MCLK as well.

The register settings in Table 879. Transmitter master mode (PLLAUDIO) are correct, the description in register TXMODE is not (says reserved).

Regards,
NXP Support.

[lpcware]

Content originally posted in LPCWare by nils28 on Tue Sep 24 03:32:32 MST 2013
Hi !

You can find the answer in Fig.125 p1038 of UM. With this scheme, you can see the PLLAUDIO route to I2S bloc. You should set respectively bit 12 and bit 13 of CREG6 for TX and RX.

Use folowing instruction :

/* Set I2S0_TX_SCK_IN_SEL : Redirect PLL0Audio to I2S_TX_MCLK */
LPC_CREG->CREG6 = (1<<12);
/* Set I2S0_RX_SCK_IN_SEL : Redirect PLL0Audio to I2S_RX_MCLK */
LPC_CREG->CREG6 = (1<<13);

Then set I2STXMODE[1:0], I2STXMODE[2], I2SRXMODE[1:0], I2SRXMODE[2] in a good way to I2S block