Setting LPC1768 I2S to work with PCM5102A

[victorcasado]

Hi,

I am developing an audio application, that by now only requires to send data from the LPC to a DAC, I am using a development board with PCM5102A that has BCLK, LRCK and DATA, I have configured pins of the LPC as follows: P0.7 to BCLK, P0.8 to LRCK and P0.9 to DATA.

Here I attach my code, what I don't know how to configure are the registers I2SIRQ, I2STXRATE, I2STXBITRATE and the ws_halfperiod of the DAO registe, I want to get 48kHz, in 16 bit Stereo, so as I have found on Google I shoud have a BCLK of 2x16x48000 = 1536000, but I don't know how to get the X and Y dividers for that.

Thank you so much

#include "LPC17xx.h"
#include "core_cm3.h"
#include "system_LPC17xx.h"

int main(){
    
}

int InitI2S_PCM5102A(){
    LPC_SC->PCONP |= (0x01<<27); //Alimentar Clock I2S
    LPC_PINCON->PINSEL0 |= ((0x01<<14) | (0x01<<16) | (0x01<<18));  //P0.7 I2STX_CLK -- P0.8 I2STX_WS -- P0.9 I2STX_SDA
    LPC_I2S->I2SDAO &= ~((0x01<<2) | (0x01<<5)); //I2S as Stereo and MASTER
    LPC_I2S->I2SIRQ |= (0x01<<1); //Enable TX I2S IRQ
    
    
    LPC_I2S->I2STXRATE = ;
    LPC_I2S->I2STXBITRATE = ;
    
    
    LPC_I2S->I2STXMODE &= ~(0x03<<0);
    NVIC_EnableIRQ(I2S_IRQn);
}

void muteTX(){
    LPC_I2S->I2SDAO |= (0x01<<15);
}

void unmuteTX(){
    LPC_I2S->I2SDAO &= ~(0x01<<15);
}

void I2S_TX_data(uint32_t data){
    LPC_I2S->I2STXFIFO = data;
}

uint8_t I2S_TX_Status(){
    return ((LPC_I2S->I2SSTATE >> 16) & 0x0F);
}

void I2S_IRQHandler(void){
    
}

[xiangjun_rong]

Hi, Victor,

If want to get 48kHz, in 16 bit Stereo, you shoud have a BCLK of 2x16x48000 = 1536000, in other worss, the I2STX_CLK is required to be 1.536MHz.

 If you use the following diagram to generate the I2S transmitter clock,

You set up the I2S module as master which means that the LPC1768 drives the TX_SCK and TX_WS signals. If you use the I2S_TX_MCLK as the clock source to generate the TX_SCK signal. Pls refer to the Fig 102.

Assume that the LPC1768 runs ins 100MHz, the I2S_PCLK is also 100MHz.

If we set up the N=1, X=2,Y=65,

The TX_REF will be 100MHz*2/(65*2)=1.538MHz.

the bit clock BCLK will be 1.538MHz. I think it approach the 1.536MHz.

Hope it can help you

BR

Xiangjun Rong