Serial NAND flash driver

[lpcware]

Content originally posted in LPCWare by cquill on Sun Aug 30 21:13:56 MST 2015
Hi there,

Serial (SPI, QSPI, SPIFI) NAND flash chips seem to be relatively new (2015?)...

Witness these parts:
Winbond W25N01/02 1/2Gb (Single/Dual/Quad SPI)
Macronix MX35LF1/2 1/2Gb (Single/Dual/Quad SPI)
Micron MT291/2/4G01 1/2/4Gb (Single/Dual/Quad SPI)

All the NXP SPIFI drivers seem to be written for interfacing to serial NOR flash ICs...
Has anyone written a SPIFI driver for any of the above-mentioned chips?

I'm using the LPC1850 - want to store code and image data on SPIFI NAND flash, boot from SPIFI NAND, copy code to SDRAM on EMC, execute from SDRAM (I think).

Cheers, Chris.
NZ Embedded Engineer.

[lpcware]

Content originally posted in LPCWare by IanB on Mon Dec 21 00:56:29 MST 2015
Thanks. They must have a sample request form somewhere. . .

I clicked three "BUY" links on their websites which lead me to Digikey, Mouser etc. whose websites said "Part not recognised".

I'm currently using a 1Gb Spansion NOR flash (which is really two 512Mb parts in one package) and the erase time is SLOW (6 minutes)

[lpcware]

Content originally posted in LPCWare by cquill on Sun Dec 20 15:58:24 MST 2015
Hello, yeah, they're not really out yet; I got a sample from the manufacturer (Winbond, and trying with Macronix). Cheers, Chris.

[lpcware]

Content originally posted in LPCWare by IanB on Sat Dec 19 13:53:50 MST 2015
How did you get these parts? Everywhere I look I have to buy 5000, but I'd just like one to make a prototype.

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Oct 06 05:45:03 MST 2015
Hello Chris,

it depends on the way you want to see it: by using the SPIFI registers you might be able to manage a memory mapped reading. But this means that you need to involve the ARM to control the registers. For XIP (execution in place) the ARM bus system together with the SPIFI logic manages that in a hardwired way. That's why I think it will not work for booting as well.

The boot ROM expects a qSPI device connected to the bus. If it detects one it knows, then it's fine. If not, it goes down to 2-bit and 1-bit interface mode and tries again. In 1-bit mode it's not important whether it is a known device, it boots with the feedback from the bootcode that this device is unknown. Then you can correct this in your application code and switch to the correct interface mode (using e.g. our SPIFI lib).

Regards,
NXP Support Team.

[lpcware]

Content originally posted in LPCWare by cquill on Mon Sep 21 22:13:55 MST 2015
Hi bavarian,

Thanks for your reply.

I understand the concept of memory mapped SPIFI devices.
I understand the 2 different ways to access an address within such a device:

1. Using Read instructions (standard SPI/QSPI)
2. Using "memory mapped" accesses (which must internally trigger the SPIFI peripheral block to issue the Read instruction currently stored in the MCMD register or access its own cached copy of previously fetched SPIFI memory, correct?)

I know #1 is possible (as you say, registers and instructions are documented...)
I'm trying to understand if it will be possible to do #2 with my device (I have Winbond W25N01GV for prototyping).

If my device requires 2 separate instructions to access a random address...
(i.e. (1) read a page into an internal chip buffer, followed by (2) read out from that buffer)
...does this totally preclude the use of the SPIFI memory mapped access?

(Unless my software keeps track of which page is currently stored inside the internal chip buffer and somehow pre-emptively issues the read-page-into-buffer instruction as required)

Also, on your point about not being possible to boot from this device; how do you know?
Where can I find detail of the boot ROM capability when it is trying to establish communications with a SPIFI device?
Surely it tries a few different common instructions (i.e. Read 03h or Fast Read 0Bh)?
How does it deal with JEDEC IDs that it does not recognise?

Anyway, thanks for your help, Chris.

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Sep 14 05:56:03 MST 2015
Hello Chris,

the trick with the SPIFI is not that it physically interfaces in a more or less serial way to the memory device, the trick is that the memory is mapped directly into the ARM memory map. This allows execution from this memory. If you use a different memory type this will not be possible. This means that you will not be able to boot from a NAND SPI flash device.
I won't exclude that you can read from such a NAND flash using the SPIFI interface (registers are documented) and a software NAND flash driver, but it's not something we will support.

Regards,
NXP Support Team