Hello,
Sorry for some delay in my reply.
I am now discussing with my colleages where the approach with a dedicated flash programm to be downloaded to the target board and run that. (we already have that function in our application)
Here is what I am doiing now:
I implemented a stop core and start core function and tried to start the (ROM) flashfunction by SWD.
The return value should become '0' (or an error code....), but my initial value of -1 on this location does not change.
1st I try the 'init' command (also the prepare / erase and programm later, but all without success
bool CSpiProgrammer::StopTheCore() {
uint32_t dataword;
bool error = false;
error |= WriteDP(DP_SELECT, MEMAP_BANK_0);
error |= WriteAP(AP_TAR, AHB_DHCSR); // 0xE000EDF0
dataword = DBGKEY | C_HALT | C_DEBUGEN;
error |= WriteAP(AP_DRW, dataword);
error |= WriteAP(AP_TAR, AHB_DEMCR); // 0xE000EDFC
error |= WriteAP(AP_DRW, 1); // VC_CORERESET
Tm0(8); // 8 bit delay
error |= WriteAP(AP_TAR, AHB_AIRCR); // 0xE000ED0C
dataword = VECTKEY | SYSRESETREQ; // VECTKEY 05FA + SYSRESETREQ
error |= WriteAP(AP_DRW, dataword);
error |= WriteDP(DP_SELECT, 0x00);
Tm0(8);
return(error);
} // StopTheCore()
bool CSpiProgrammer::StartTheCore() {
uint32_t dataword;
bool error = false;
error |= WriteDP(DP_SELECT, MEMAP_BANK_0);
error |= WriteAP(AP_TAR, AHB_DHCSR); // 0xE000EDF0
dataword = DBGKEY | 0x0000 | C_DEBUGEN; // clear the C_HALT bit
error |= WriteAP(AP_DRW, dataword);
error |= WriteAP(AP_TAR, AHB_DEMCR); // 0xE000EDFC
error |= WriteAP(AP_DRW, 0); // VC_CORERESET -> OFF
dataword = VECTKEY | VECTRESET; // VECTKEY 05FA + SYSRESETREQ //0x0004;
error |= WriteAP(AP_TAR, AHB_AIRCR); // 0xE000ED0C
error |= WriteAP(AP_DRW, dataword); // 0x05FA0004);
Tm0(8); // 8 bit delay
return(error);
} // StartTheCore()
/*............part of main program..............*/
StopTheCore();
flashAddr = 0x1b000000; // flash bank2 (sector 0)
error = ReadArray(flashAddr, (uint32_t *)data, 15); // see, what's on flashAddr now
error = FPenable(); // Flash Port enable
error = ReadWord(ROM_TABLE, &flashFunc); // get the flashAddres = IAP flash calls (0x1040bfdd)
flashFunc = flashFunc & 0xfffffffe; // necessary?
error = WriteCoreReg(REG0, RAM_TARGET); // Reg 0 input structure
error = WriteCoreReg(REG1, RAM_TARGET + 32); // Reg 1 output structure
WriteWord(RAM_TARGET, 49); // init command (RAM TARGET = 0x20008e00)
WriteWord(RAM_TARGET+4, 0); // future....
WriteWord(RAM_TARGET+8, 0);
WriteWord(RAM_TARGET+12, 0);
WriteWord(RAM_TARGET+16, 0);
WriteWord(RAM_TARGET+32, -1); // clear the return value (0x20008e20 = -1)
error = WriteWord(AHB_VTOR, RAM_TARGET); // VTOR start RAM address code (0x20008000)
// some checks
error = ReadWord(RAM_TARGET+32, &retVal); // check return value still is -1
error = ReadArray(RAM_TARGET, data_flash, 5); // double check input structure
error = WriteCoreReg(REG_SP, RAM_STACK); // Give some stack space (RAM_STACK = 0x20008ff0)
error = WriteCoreReg(REG_PC, flashFunc); // PC counter points to flah function in ROM (0x1040bfdc)
error = StartTheCore();
retry = 10;
error = ReadWord(RAM_TARGET+32, &retVal);
while(retVal && retry) {
Delayt(1); // short delay
retry--;
error = ReadWord(RAM_TARGET+32, &retVal);
}
error = StopTheCore();
// next commands......
/*...........etc etc.............*/