SSP interrupt at transfer end

[lpcware]

Content originally posted in LPCWare by jokn on Thu Jan 10 05:05:09 MST 2013
Is it really true?
Does the SSP interface has no interrupt for the transmit fifo empty event or for transfer empty? The SPI interface has, but I cannot use the SPI interface because the pins a used from SPIFI.

So in my distress I have to start a timer to get an interrupt at transfer end.
Or as somebody a better idea?
Please don't ask me why I use a transfer end interrupt. This is because a scan several SPI slave and I have to change the select signal by gpio.

[lpcware]

Content originally posted in LPCWare by jokn on Fri Feb 22 12:39:53 MST 2013
Hi Dave,

I solved this problem by using one of the sgpio timers. Because I do not use the sgpio feature. The Timer gives me the interrupt for the end of transfer. The advantage of using the sgpio timer is that you have a prescaler and a timer for every bit. So it is very easy to set the timer for different bit rates.

Regards
Josef

[lpcware]

Content originally posted in LPCWare by nxp21346 on Tue Jan 15 14:47:03 MST 2013
The BUSY bit should be useful to determine whether the SSP is done transmitting. An interrupt can be generated when the FIFO is half empty or by a timer, then the BUSY bit can be checked to see if the SPI is done transmitting.

-Dave @ NXP