I am using SSP0 on the LPC4088 with SSP_FRAMEFORMAT_SPI and experiencing similar issues.
It appears the LPC4088 shifts a frame in/out of the FIFO whenever the chip select goes from the low state to the high state.
I believe for SPI communication the chip select is normally held low for the duration of a transaction (multiple frames) but for some reason the LPC4088 instead uses the chip select to indicate the transmission of a single frame.
I am using a Linux device as the master and ioctl to send SPI messages, looks like I might have to set up a new transmission for every frame.
Also, the interrupts offered by the SSP are not useful if I want to load a new transmission frame based on a received frame, normally for SPI peripherals you would expect to have an interrupt when a new frame has been received but the interrupts for the SSP lack this. Looks like I will instead have to use a GPIO interrupt on the chip select line (a long with the chip select line being toggled between every frame) to load the next transmission frame into the FIFO.
After discussion with colleagues it appears the chip select behaviour actually depends on the values used for clock polarity and clock phase (bad chip design?).
Setting up the SSP with the clock phase bit (CPHA) set allows continuous data transfers to occur.
The functions Chip_SSP_GetStatus, Chip_SSP_ReceiveFrame, and Chip_SSP_SendFrame can then be used to read the FIFO as data enters and write out new data immediately.
___ ___ \ / SSEL \ / \_____________________________/ #### #### #### #### Clk #### #### #### #### _________####___####___####___####______ ______ ____ ____ ____ ____ ___ \ / \ / \ / \ / \ / MOSI * X cmd X * X * X * X * ______/ \____/ \____/ \____/ \____/ \___ ______ ____ ____ ____ ____ ___ \ / \ / \ / \ / \ / MISO * X * X dat0 X dat1 X dat2 X * ______/ \____/ \____/ \____/ \____/ \___ |