SSP as SPI- Chip Enable

[lpcware]

Content originally posted in LPCWare by akshimmu on Tue Apr 19 04:22:31 MST 2016
If a pin is configured as a SSP CE pin and not a GPIO pin, does the SSP take care of how long the pin must remain low? Because, im using SST25VF010A to store and read data via SPI, and the datasheet says that during Read operation if the CE remains low, data will be continuously outputted from the Flash. How does the SSP know how many bytes i want to read? So musn't the CE be controlled by the user??

[lpcware]

bump

[lpcware]

Content originally posted in LPCWare by akshimmu on Thu Apr 21 21:45:59 MST 2016
Il try using it as a SSSPSEL pin first. If it fails,il use it as a GPIO.
Thanks :)

[lpcware]

Content originally posted in LPCWare by IanB on Thu Apr 21 04:55:05 MST 2016
Yes - they may have fixed it for the LPC17, but I couldn't get it to work on the LPC15
(see https://www.lpcware.com/content/forum/spi-ssel-control)

I worked it as a GPIO line, and I checked the idle flag in the SPI before sending it high again.

[dimitrissideris]

Hi there,

Do you mean the BSY bit of status register?

Do u have any sample code that works?

thanx

[lpcware]

Content originally posted in LPCWare by akshimmu on Wed Apr 20 03:36:16 MST 2016
So your saying, make CS as gpio>Make low>Transmit data>Make high after completion?
Dont make CS as SSP CS(SSEL)?

[lpcware]

Content originally posted in LPCWare by IanB on Wed Apr 20 00:46:54 MST 2016
If it's anything like the LPC15xx then no, it doesn't, it just makes a mess of it; and if there are interrupts in use elsewhere, it gets into a compete shambles, de-asserts CS too early and you end up reading 0xFF when you think you are reading data.

Eventually after hours of trying to get it to work, I gave up and controlled CS manually