I am using LPC4367 for my product development. I refered the code for EMC interface. But after interfacing code the and debugging i am facing follwing issue when I interfaced SRAM (IS64WV12816DBLL).
When I write the data then it shows the data is written in it after viewing the memory monitoring.but after goin for othe location it again becomes FFFF, Following is the initialization code for my test code.
#define CLK0_DELAY 7
STATIC const IP_EMC_STATIC_CONFIG_T S29GL064S_config =
{
0,
EMC_STATIC_CONFIG_MEM_WIDTH_16 |
EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
EMC_STATIC_CONFIG_BLS_HIGH/* |
EMC_STATIC_CONFIG_PAGE_MODE_ENABLE |
EMC_CONFIG_BUFFER_ENABLE*/,
EMC_NANOSECOND(45),
EMC_NANOSECOND(35),
EMC_NANOSECOND(45),
EMC_NANOSECOND(35),
EMC_NANOSECOND(35),
EMC_CLOCK(4)
};
void EMC_SetupSRAMMemmory(void)
{
/* Setup EMC Delays */
/* Move all clock delays together */
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
/* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
less than 120MHz, a divider of 1 or 2 is ok. */
//Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG |= (1 << 5);
LPC_CREG->CREG6 |= (1 << 16);
/* Enable EMC clock */
Chip_Clock_Enable(CLK_MX_EMC);
/* Init EMC Controller -Enable-LE mode */
Chip_EMC_Init(1, 0, 0);
/* Init EMC Static Controller CS0 */
Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &S29GL064S_config);
LPC_EMC->STATICCONFIG0 |= 1 << 19;
}
/*Main Code */
#define SRAM_SIZE_BYTES (2*1024)
#define SRAM_SIZE SRAM_SIZE_BYTES
int main(void)
{
uint16_t *sram = (uint16_t *)(EMC_ADDRESS_CS0); /* SDRAM start address. */
uint32_t index, i;
uint32_t sramAddr;
uint16_t Data = 0XA5A5;
uint16_t Data1 = 0x5A5A;
uint8_t Flag = 0;
uint32_t *sram12= (uint16_t *)(EMC_ADDRESS_CS0);
for (index = 0; index < (SRAM_SIZE ); index++)
{
Chip_GPIO_SetPinToggle(LPC_GPIO_PORT, 5, 5);
if(Flag == 0 )
{
sramAddr = Data;
*(uint16_t *)(sram + index ) = sramAddr;
Flag = 1;
}
else
{
sramAddr = Data;
*(uint16_t *)(sram + index ) = sramAddr;
Flag = 0;
}
if(*(uint16_t *)(sram + index ) != sramAddr )
{
while(1);
}
}
}/* EOF Main*/
I have attached the test code for your reference, Please let know if there is anything missing. It is in higher priority.
Also share any reference code for SRAM interface with LPC43XX.
Thanks
Gaurav More
Hi,
Could you confirm if this issue is the same than this https://community.nxp.com/message/1114450 ?
Regards
Soledad
Hi Soledad,
Thanks for the reply,
After checking the code I found some mistakes like I mssing the CS0 initialization and also the frequency was 2MHz after that I changed the MAX_CLOCK_FREQ to 40MHz then it started writing with EMCCLK 20MHz and I can see in the memory monitoring .
The SRAM is interfaced properly and is working. The problem was with the hardwre connection. I made it proper and then it worked.
But now I have tested it with lower frequency that is 20MHz. and with wire connection. We are going to use SDRAM and SRAM both. For finalizing the design I need some reference or application note. Currently I am referring AN11508 application note for our refrence.
Kindly suggest if there is any specific reference for interfacing both.
I am using LPC4367JBD208E controller and considering the same please guide us reagrding the peripheral connections.
Thanks
Gaurav More
Hi,
Access to external memory is standardized for any microcontrollers (including NXP MCUs)
Each address is accessing the data width size of the memory. For example, if you configure the MCU to use 16-bits width SRAM, address 0x00 will access 16-bits data located in address 0x00, address 0x01 will access 16-bits data located in address 0x01 (If you view it in bytes, address 0x00 will access data at address 0x00, 0x01. And address 0x01 will access data at address 0x02 and 0x03, etc).
The memory (and the MCU) has LOW_Byte and HIGH_Byte mask pin to mask the unwanted data. So, if the MCU wants to write 8-bits to upper address 0x00 (in bytes, write to address 0x01), it will use the LOW_BYTE mask to mask the unnecessary lower 8-bits.
Please check the following threads,
External SRAM data handling issue
In addition, please check the following schematic file
https://www.nxp.com/downloads/en/design-support/Hitex-LPC1850-4350-Schematics.pdf
I hope this helps,
have a nice day!
Regards
Soledad
Hi Soledad,
Thanks for the reply.
I have gone through https://community.nxp.com/thread/418398 link for SRAM. We need to check both SDRAM and SRAM access. As per the Application note AN115088 it is suggested to use buffer IC between the Controller and SRAM and direct connection between controller and SDRAM.
This is regarding the schematic but regarding the PCB guidelines need you inoput and suggestion or any reference.Mean while I will check the link you shared.
Thanks
Gaurav More
Hi,
Please check the following application notes:
https://www.nxp.com/docs/en/application-note/AN10935.pdf
https://www.nxp.com/docs/en/application-note/AN10778.pdf
I hope this helps,
Regards
Soledad
Hi Soledad,
Thanks for the reply,
The PCB layout application note shared is for BGA packages. We will be using LQFP package. LPC4367JBD208E is the controller part number which we are using,
Please share the application note for PCB layout for LQFP packages.
Thanks
Gaurav More
Hi,
Please check the following application note
https://www.nxp.com/docs/en/application-note/AN4388.pdf
regards
Soledad