Hello Ratheesh T,
Answer your two questions:
1. SPI can't receive the correct data in the periph_spi_sm_int sample code
Answer: The solution is making SPI SLAVE IRQ has higher priority than master IRQ
Please add these codes before while(loop) :
NVIC_SetPriority(LPC_SPIMASTERIRQNUM, 2);
NVIC_SetPriority(LPC_SPISLAVEIRQNUM, 1);
/* Enable SPI controller interrupts */
NVIC_EnableIRQ(LPC_SPIMASTERIRQNUM);
NVIC_EnableIRQ(LPC_SPISLAVEIRQNUM);
It just like this:

At last, the printf data is:

2. call the function setupMaster()
Actually, just like the official code, you just need to call setupMaster() once, then you don't need to call it any more.
I have test it on my side, after add the item 1 code.
each time, I will get the correct data.
These are the three round test result:
SPI master/slave combined example
SLAVE [txDoneCount = 17, rxDoneCount = 16]
MASTER [txDoneCount = 16, rxDoneCount = 16]
TRANSFER COMPLETE: errors = 0
Master total transfer time = 17104uS
Showing data from : Master TX data
0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008
0x0009 0x000a 0x000b 0x000c 0x000d 0x000e 0x000f 0x0010
Showing data from : Master RX data
0xfffe 0xfffd 0xfffc 0xfffb 0xfffa 0xfff9 0xfff8 0xfff7
0xfff6 0xfff5 0xfff4 0xfff3 0xfff2 0xfff1 0xfff0 0xffef
Showing data from : Slave TX data
0xfffe 0xfffd 0xfffc 0xfffb 0xfffa 0xfff9 0xfff8 0xfff7
0xfff6 0xfff5 0xfff4 0xfff3 0xfff2 0xfff1 0xfff0 0xffef
Showing data from : Slave RX data
0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008
0x0009 0x000a 0x000b 0x000c 0x000d 0x000e 0x000f 0x0010
SLAVE [txDoneCount = 17, rxDoneCount = 16]
MASTER [txDoneCount = 16, rxDoneCount = 16]
TRANSFER COMPLETE: errors = 0
Master total transfer time = 17102uS
Showing data from : Master TX data
0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018
0x0019 0x001a 0x001b 0x001c 0x001d 0x001e 0x001f 0x0020
Showing data from : Master RX data
0xffee 0xffed 0xffec 0xffeb 0xffea 0xffe9 0xffe8 0xffe7
0xffe6 0xffe5 0xffe4 0xffe3 0xffe2 0xffe1 0xffe0 0xffdf
Showing data from : Slave TX data
0xffee 0xffed 0xffec 0xffeb 0xffea 0xffe9 0xffe8 0xffe7
0xffe6 0xffe5 0xffe4 0xffe3 0xffe2 0xffe1 0xffe0 0xffdf
Showing data from : Slave RX data
0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018
0x0019 0x001a 0x001b 0x001c 0x001d 0x001e 0x001f 0x0020
SLAVE [txDoneCount = 17, rxDoneCount = 16]
MASTER [txDoneCount = 16, rxDoneCount = 16]
TRANSFER COMPLETE: errors = 0
Master total transfer time = 17102uS
Showing data from : Master TX data
0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028
0x0029 0x002a 0x002b 0x002c 0x002d 0x002e 0x002f 0x0030
Showing data from : Master RX data
0xffde 0xffdd 0xffdc 0xffdb 0xffda 0xffd9 0xffd8 0xffd7
0xffd6 0xffd5 0xffd4 0xffd3 0xffd2 0xffd1 0xffd0 0xffcf
Showing data from : Slave TX data
0xffde 0xffdd 0xffdc 0xffdb 0xffda 0xffd9 0xffd8 0xffd7
0xffd6 0xffd5 0xffd4 0xffd3 0xffd2 0xffd1 0xffd0 0xffcf
Showing data from : Slave RX data
0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028
0x0029 0x002a 0x002b 0x002c 0x002d 0x002e 0x002f 0x0030
SLAVE [txDoneCount = 17, rxDoneCount = 16]
MASTER [txDoneCount = 16, rxDoneCount = 16]
TRANSFER COMPLETE: errors = 0
Master total transfer time = 17102uS
Showing data from : Master TX data
0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038
0x0039 0x003a 0x003b 0x003c 0x003d 0x003e 0x003f 0x0040
Showing data from : Master RX data
0xffce 0xffcd 0xffcc 0xffcb 0xffca 0xffc9 0xffc8 0xffc7
0xffc6 0xffc5 0xffc4 0xffc3 0xffc2 0xffc1 0xffc0 0xffbf
Showing data from : Slave TX data
0xffce 0xffcd 0xffcc 0xffcb 0xffca 0xffc9 0xffc8 0xffc7
0xffc6 0xffc5 0xffc4 0xffc3 0xffc2 0xffc1 0xffc0 0xffbf
Showing data from : Slave RX data
0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038
0x0039 0x003a 0x003b 0x003c 0x003d 0x003e 0x003f 0x0040
I also attached my modified code for your reference.
Wish it helps you!
Please try again, if you still have question, please let me know.
Have a great day,
Kerry
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