[SOLVED] LPC11U67 System PLL won't lock.

[lpcware]

Content originally posted in LPCWare by acker10 on Thu Apr 17 23:19:50 MST 2014
I'm trying to follow the directions in the LPC11U6x user manual for basic clock configuration.

Debugger shows that my loop to check the System PLL status (SYSPLLSTAT) register for a PLL lock is never exiting.  (Section 4.4.4 in the user manual.)

What are the debugging steps for this kind of problem?

I've used this same crystal on a LPC11U37 with same circuitry without problems.  Bad solder joint on XTALOUT/XTALIN pins (LQFP48)?  Not the right capacitor values?  Perhaps the LPC11U67is more picky about crystal accuracy than the LPC11U37 was?  (No, I don't have an oscilloscope unfortunately.)  My code is bad?  (Bad MSEL/PSEL selection?)

The crystal is 12mhz with two 18pF capacitors.

Here's the code:

void setupClock()
{
  LPC_SYSCON->PDRUNCFG_b.SYSPLL_PD = 0; // 0=powered, 1=off
  LPC_SYSCON->SYSPLLCLKSEL = 1; // 0=irc, 1=systemosc, 3=32khzclk

  LPC_SYSCON->SYSPLLCLKUEN = 1;
  LPC_SYSCON->SYSPLLCLKUEN = 0;
  LPC_SYSCON->SYSPLLCLKUEN = 1;
  while(!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); // this works

  // must admit not sure this is right
  LPC_SYSCON->SYSPLLCTRL_b.MSEL = 3;
  LPC_SYSCON->SYSPLLCTRL_b.PSEL = 1;

  while(!(LPC_SYSCON->SYSPLLSTAT & 0x01)); // **this is where it never exits**
}

Thanks.

[lpcware]

Content originally posted in LPCWare by Belias on Mon Jun 30 07:52:18 MST 2014
Had the same problem, luckily I found this post after SIX HOURS ... ... ...

Now it works, but of course I was suspecting my hardware. Please NXP update all these errors in the Datasheet!

[lpcware]

Content originally posted in LPCWare by acker10 on Sat Apr 19 13:28:13 MST 2014
Finally able to figure this out.

I was missing a few things, but the thing that held me up the longest was missing the ADMODE bit in the IOCON registers for PIO2_0 and PIO2_1 (table 88 in the user manual).
The LPC11U67 defaults to "disabled analog mode."  The crystal didn't start working until I set this bit to "enable analog mode."

What's interesting is if you use SVDConv from ARM CMSIS package on the version 0.6 lpc11u6x SVD file downloadable on this site, the PIO2_0_b and PIO2_1_b ICON structures have fields for everything but ADMODE, so you have to use LPC_IOCON->PIO2_0 and LPC_IOCON_PIO2_1 instead to set the whole bitfield at once.

By the way, I also think there's an error in the user manual. 
Section 4.2.3 states:

---

Quote:

1. In the IOCON block, disable the pull-up and pull-down resistors in the IOCON
registers for pins PIO2_0 and PIO2_1 and set the MODE bits to 0x1.

---

Setting MODE to 0x1 is wrong.  MODE should be 0 to disable the pull-up and pull-down.  Instead it should be "set the FUNC bits to 0x1."  This held me up for awhile too until I figured out this mistake in the documentation.

Minimal routines that got me going:

void setupSystemOscillator()
{
  LPC_SYSCON->SYSAHBCLKCTRL_b.IOCON = 1;
  LPC_IOCON->PIO2_0 = 1;
  LPC_IOCON->PIO2_1 = 1;
  LPC_SYSCON->PDRUNCFG_b.SYSOSC_PD = 0;
  int i;
  for(i = 0x1000; i > 0; i--) {
    asm("movs r0, r0"); // noop delay
  }
}

void setupClock()
{
  setupSystemOscillator();

  LPC_SYSCON->SYSPLLCLKSEL = 1;
  LPC_SYSCON->SYSPLLCLKUEN = 0;
  LPC_SYSCON->SYSPLLCLKUEN = 1;

  LPC_SYSCON->PDRUNCFG_b.SYSPLL_PD = 1;
  LPC_SYSCON->SYSPLLCTRL_b.MSEL = 0;
  LPC_SYSCON->SYSPLLCTRL_b.PSEL = 3;
  LPC_SYSCON->PDRUNCFG_b.SYSPLL_PD = 0;
  while((LPC_SYSCON->SYSPLLSTAT & 0x01) != 1);
}