I would like some help for the an11343 example code implementation.
The example is a dual core M0-M4 implementation.
The SGPIO interrupt handler lies inside M0 example code and it handles the sgpio interrupts. The slice and pin configuration of sgpio lie in M4 example code. Ok straight forward.
I see that in M4 example code there is a Gpio interrupt handler which is actually the VSYNC interrupt hanlder. (Vsync is connected to gpio pin not sgpio).
// GPIO IRQ slot 6 is used by VSync IRQ, common to all cameras
void ATR_RAMCODE GPIO6_IRQHandler(void)
{
LPC_GPIO_PIN_INT_Type *pPinInt = LPC_GPIO_PIN_INT;
// leave M0 to process GPIO6 int
if (pPinInt->RISE & BVON(PIQ_VSYNC))
{
// rising edge
// previous frame is completed
pPinInt->RISE = BVON(PIQ_VSYNC);
NVIC_DisableIRQ(SGPIO_IINT_IRQn);
SGPStop();
s_ccb.vsyncCnt++;
// judge whether is the previous frame is received
if (s_ccb.sgpIntPerFra != 0)
{
__set_PRIMASK(1);
s_ccb.rdyRxBufCnt++;
#if 0 == IS_TWIN_RXBUF
#else
s_ccb.rcvTglBit ^= 1;
#endif
__set_PRIMASK(0);
s_ccb.vsyncEffCnt++;
s_ccb.sgpIrqCntInPrevFra = s_ccb.sgpIntPerFra;
}
s_ccb.sgpIntPerFra = 0;
if (s_ccb.freeRxBufCnt)
s_ccb.freeRxBufCnt--;
#if 0 == IS_TWIN_RXBUF
s_ccb.pBuf = s_ccb.pRcvDbBuf->aa32[0];
#else
s_ccb.pBuf = s_ccb.pRcvDbBuf->aa32[s_ccb.rcvTglBit];
#endif
s_ccb.pBufEnd = s_ccb.pBuf + (CAP_BUF_SIZE / 4);
SGPGetRdyToGo();
__sev();
}
}
There is some comment " // leave M0 to process GPIO6 int".
Is this true;
If not and comments are wrong,
sgpio interrupt hander is in M0 code and gpio handler for vsync is in M0?
