Content originally posted in LPCWare by MikeSimmonds on Mon Oct 12 17:17:29 MST 2015
The documentation for physical integration of SDRAM address lines seems to be univerally confusing in the NXP manuals!
We had to redesign our board because of that.
NB: We use 1778 so please double check with the relevant UM.
As far as I know, A13 and (for 4 banks) A14 are always used for the bank select lines and A0 to A??
(depending on the columns on the actual device) for row and column addressing.
See these app notes for better understanding (they are for different families, but are probably the same EMC peripheral?).
A10771, A10935, and AN10950.
For what it is worth, I attach our setup. Using two 16-bit wide devices to get a 32-bit wide memory interface. [32 MB]
Cheers, Mike.