SDRAM Reference code for Understanding the functionality

[gauravmore]

 Hi Jeremy, 

I am using LPC4367 controller with MCU Xpresso 10.3.0_2200. I am using SDRAM and NOR Flash interface in one of our projects. I was working with Evaluation board OM13088 but it that board no SDRAM and NOR flash interface is avialable.  I am using SDRAM and NOR flash both interfaced with EMC lines aviable in LPC4367 controller.

I refered the code in e lpcopen_3_02_lpcxpresso_mcb4357 and also refered periph_memtest and misc_spifi_tst demos. But there is no EMC init routine avialable. Is there any sample code or a reference code for SDRAM with proper intitiatilization routine.

Also i want to allocate one of my Buffer to SDRAM address, i got the information related to it i MCU expresso User guied but still i want to know than as we user 

__At(Address) attribute in Keil to allocate the array or a buffer like

uint16_t Buffer[1024]                     __at(0x28000000) 

In the similar manner how we can use it in MCU Expresso . I have  downloaded MCUxpresso 10.3.0 . 

To conclude i want the sample or areference code for SDRAM and NOR flash with proper EMC init routine which not provided in existing reference code

I need this since i want to test my development board which is ready. So please consider it on higher priority. Mean while i am trying to refere other forums as well for my understanding.

Thanks 

Gaurav More

[gauravmore]

Hi Jeremy,

Sorry for the late response. As per  your inputs i have check the code for SDRAM available in LPCopen (periph_memtest) ans as per that I created new project for my development board using LPC4367 in LPCXpresso IDE

I am facing issue with the code where my code crashes in between.  Following the code for EMC initialization.

SDRAM which  i habe interface is "AS4C4M16SA-C&I"  64M – (4M x 16 bit) Synchronous DRAM (SDRAM). Controller is running at 100 Mhz.

#define EMC_ADDRESS_DYCS0   (0x28000000)

#define DRAM_SIZE 20//(8 * 1024 * 1024)

/* EMC clock delay */
#define CLK0_DELAY 7

void Chip_SystemInit(void)
{
/* Initial internal clocking */
//Chip_SetupIrcClocking();

/* Setup FLASH acceleration to target clock rate prior to clock switch */
Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);

Chip_SetupXtalClocking();

/* Reset and enable 32Khz oscillator */
LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
}

void EMC_SetpinMux

{

/* EMC Address Lines */
/*A0 - A4*/
Chip_SCU_PinMuxSet(0x02, 9, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x02, 10, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x02, 11, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x02, 12, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x02, 13, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*A5 - A7*/
Chip_SCU_PinMuxSet(0x01, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x01, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x01, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));

/*A8 - A10*/
Chip_SCU_PinMuxSet(0x02, 8, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x02, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x02, 6, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*A11 - A13*/
Chip_SCU_PinMuxSet(0x02, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x02, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x02, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));

/*A14-A15*/
Chip_SCU_PinMuxSet(0x06, 8, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1));
Chip_SCU_PinMuxSet(0x06, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1));

/* EMC Data Lines */
/* D0 - D7 */
Chip_SCU_PinMuxSet(0x01, 6, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x01, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x01, 8, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x01, 9, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x01, 10, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x01, 11, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x01, 12, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
Chip_SCU_PinMuxSet(0x01, 13, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/* D8 - D11 */
Chip_SCU_PinMuxSet(0x05, 4, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x05, 5, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x05, 6, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x05, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));

/* D12 - D15 */
Chip_SCU_PinMuxSet(0x05, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x05, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x05, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));
Chip_SCU_PinMuxSet(0x05, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2));

/*EMC Control Lines*/
/*EMC_WE*/
Chip_SCU_PinMuxSet(0x01, 6, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*EMC_BLS0*/
Chip_SCU_PinMuxSet(0x01, 4, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));
/*EMC_BLS0*/
Chip_SCU_PinMuxSet(0x06, 6, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1));

/*EMC_CAS*/
Chip_SCU_PinMuxSet(0x06, 4, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*EMC_RAS*/
Chip_SCU_PinMuxSet(0x06, 5, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*SDRAM_CS0*/
Chip_SCU_PinMuxSet(0x06, 9, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*SDRAM_CKEO (EMC_CKEOUT0)*/
Chip_SCU_PinMuxSet(0x06, 11, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*EMC_DQMOUT0*/
Chip_SCU_PinMuxSet(0x06, 12, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/*EMC_DQMOUT1*/
Chip_SCU_PinMuxSet(0x06, 10, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3));

/* SDRAM_CLK0 (EMC_CLK0)*/
Chip_SCU_ClockPinMuxSet(0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0));

}

void EMC_SetupSDRAMMemmory(void)
{

/* Setup EMC Delays */
/* Move all clock delays together */
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));

/* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
less than 120MHz, a divider of 1 or 2 is ok. */
Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
LPC_CREG->CREG6 |= (1 << 16);

/* Enable EMC clock */
Chip_Clock_Enable(CLK_MX_EMC);

/* Init EMC Controller -Enable-LE mode */
Chip_EMC_Init(1, 0, 0);
/* Init EMC Dynamic Controller */
Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &AS4C4M16SA_CI_Config);

}

/*Main While*/

uint32_t *StardAddr, *StardAddr1;
uint32_t Length = DRAM_SIZE;
uint32_t ReadData[DRAM_SIZE];
uint32_t WriteData[DRAM_SIZE];
unsigned long i = 0;

int main(void)
{

#if defined (__USE_LPCOPEN)
// Read clock settings and update SystemCoreClock variable
SystemCoreClockUpdate();

#endif

// TODO: insert code here
/* LED31 PA.4 - GPIO5[19] */
Chip_SCU_PinMuxSet(0xA, 4,(SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4));
Chip_GPIO_SetPinState(LPC_GPIO_PORT, 5, 19, (bool) true);
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 19);

EMC_SetPinMux();
// Force the counter to be placed into memory
EMC_SetupSDRAMMemmory();
// Enter an infinite loop, just incrementing a counter

while(1)
{
StardAddr = (uint32_t *)EMC_ADDRESS_DYCS0;
for(i=0; i<20; i++)
{
*StardAddr = 0x55AA55AA;
StardAddr++;
}
for (i=0; i<0xFFFF;i++ );
for (i=0; i<0xFFF;i++ );
#if 1
StardAddr1 = (uint32_t *)EMC_ADDRESS_DYCS0;
for(i=0; i<Length; i++)
{
ReadData[i] = (uint32_t)*StardAddr1;
if(ReadData[i] != *StardAddr1)
{
while(1)
{
Chip_GPIO_SetPinToggle(LPC_GPIO_PORT, 5, 19);
for (i=0; i<0xFFFFF;i++ );
}
}
StardAddr1++;
}
#endif

}
return 0 ;
}

I am not understanding that it sometimes works and sometime while debugging it crasches. I referred  follwing thread

https://community.nxp.com/thread/455171 while implementation. 

Please let me now whether the method whic i am using to access the SDRAM memory is correct?

Also find the code attached for reference.

Thanks 

Gaurav More

[gauravmore]

Hi Jeremy,

Please refer the issue link mentioned .

https://community.nxp.com/t5/LPC-Microcontrollers/Issue-in-Allocation-of-Variable-in-External-RAM-SD...

Kindly reply for the same.

BR,

Gaurav More

[gauravmore]

Hi Jeremy,

Any inputs regarding the query. It is required for  the project development. Need to any modifications required since some times it runs a complete while and agian while repeating the same statement it crashes,

while(1)
{
StardAddr = (uint32_t *)EMC_ADDRESS_DYCS0;
for(i=0; i<20; i++)
{
*StardAddr = 0x55AA55AA;
StardAddr++;
}
for (i=0; i<0xFFFF;i++ );
for (i=0; i<0xFFF;i++ );
#if 1
StardAddr1 = (uint32_t *)EMC_ADDRESS_DYCS0;
for(i=0; i<Length; i++)
{
ReadData[i] = (uint32_t)*StardAddr1;
if(ReadData[i] != *StardAddr1)
{
while(1)
{
Chip_GPIO_SetPinToggle(LPC_GPIO_PORT, 5, 19);
for (i=0; i<0xFFFFF;i++ );
}
}
StardAddr1++;
}
#endif

refer the code attached inthe above post.

Thanks 

Gaurav More