SCT counter. Difference use bottom/upper half.

[jirisvabik]

Hi guys. I have a problem with SCT counter. When I use the lower 1/2 to generate a pulse, everything works OK. When I use upper 1/2, output is dumb. What's the difference? Who bit I forget set up?

void InitCppm(void)
{
Chip_SWM_MovablePinAssign(SWM_SCT_OUT0_O, ); /*GPIO P0_0*/
Chip_SCT_Init(LPC_SCT);

Chip_SCT_Init(LPC_SCT);

Chip_SCT_Config(LPC_SCT, SCT_CONFIG_16BIT_COUNTER );

Chip_SCT_SetMatchCountH(LPC_SCT, SCT_MATCH_0, 0x9F00);
Chip_SCT_SetMatchReloadH(LPC_SCT, SCT_MATCH_0, 0x9F00);

Chip_SCT_SetOutput(LPC_SCT, SCT_OUTPUT_0, SCT_EVT_0 );
Chip_SCT_ClearOutput(LPC_SCT, SCT_OUTPUT_0, SCT_EVT_1);

Chip_SCT_Output(LPC_SCT, SCT_EVT_0);

Chip_SCT_EventState(LPC_SCT, SCT_EVENT_0, ENABLE_STATE0);
Chip_SCT_EventControl(LPC_SCT, SCT_EVENT_0, (CHIP_SCT_EVENTCTRL_T)( SCT_EVECTRL_MATCH0 |
SCT_COMBMODE_MATCH |
SCT_HEVENT_H |
SCT_STATELD_1 |
SCT_STATEEV_1 ));

Chip_SCT_EventState(LPC_SCT, SCT_EVENT_1, ENABLE_STATE1);
Chip_SCT_EventControl(LPC_SCT, SCT_EVENT_1, (CHIP_SCT_EVENTCTRL_T)( SCT_EVECTRL_MATCH0 |
SCT_COMBMODE_MATCH |
SCT_HEVENT_H |
SCT_STATELD_1 |
SCT_STATEEV_0 ));

LPC_SCT->LIMIT_H = 0x00000003;

Chip_SCT_ClearControl(LPC_SCT , SCT_CTRL_HALT_H);
}

[jirisvabik]

I found it. In function Chip_SCT_EventControl need added | SCT_OUTSEL_H

[jeremyzhou]

Hi Jiri Svabik,

I'm glad to hear that you had already solved this issue, if you have any question, just feel free to contact with me.
Have a great day,
Ping

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[jirisvabik]

Thank you for your insights and ideas. JS