LPC1769:
* CPU clock frequency = 100MHz
* PCLK_SPI=1; //so peripheral clk also 100MHz
1. What value can put in S0SPCCR for getting Max. SCLK frequency for 18ADC(500KSPS and Its neeed 34 pulse for per sampling).
2. In S0SPCCR register what value can choose, based on what parameters?
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Hi,
I do not know if this is your scenario, pls clarify. You use external ADC with SPI interface which functions as slave spi, the ADC conversion rate is dependent on the SCK clock frequency, as you said that one ADC conversion requires 34 SCK clock cycles, am I right? If it is the case, the 0.5MSPS conversion rate requires that the SCK clock frequency is 0.5MHz*34=17MHz, it is okay if you configure the SCK as 17mhz.
BTW, I have checked the data sheet of LPC176x, the maximum SCK clock frequency of SPI module in master mode is 12.5MHz. The maximum SCK clock frequency for SSP module is 33MHz, I assume that you can use SSP module to communicate with the slave SPI module if the SCK is required to be 17mhz.
If it is convenient, can you tell us the ADC part number so that we can have a check?
BR
XiangJun Rong
Hi,
I do not know if this is your scenario, pls clarify. You use external ADC with SPI interface which functions as slave spi, the ADC conversion rate is dependent on the SCK clock frequency, as you said that one ADC conversion requires 34 SCK clock cycles, am I right? If it is the case, the 0.5MSPS conversion rate requires that the SCK clock frequency is 0.5MHz*34=17MHz, it is okay if you configure the SCK as 17mhz.
BTW, I have checked the data sheet of LPC176x, the maximum SCK clock frequency of SPI module in master mode is 12.5MHz. The maximum SCK clock frequency for SSP module is 33MHz, I assume that you can use SSP module to communicate with the slave SPI module if the SCK is required to be 17mhz.
If it is convenient, can you tell us the ADC part number so that we can have a check?
BR
XiangJun Rong