Reset LPC43XX M4 to boot from SRAM, skipping boot ROM

[gertvierman]

For our product we would like to be able to put the M4 core to sleep, have the M0 load new code from flash to RAM, and then reset the M4 to run the new code from RAM.

The LPC43xx manual states that the M4MEMMAP is default set to the boot rom at 0x1040 000; Is this default value only set at system reset, or also when the M4 is reset with M4_RST in LPC_RGU->RESET_CTR?

[bernhardfink]

• When you perform a system reset or a power-on reset the LPC4300 always starts with the Cortex-M4, executing the boot ROM code located at 0x0104 0000 
• If you issue a M4_RST, from the M4 itself or from the M0APP, you start over with a MASTER_RESET, also executing the bootcode
• But you could think of a tricky implementation where you put the M4 in stop, replace the code and then wake it up again. No idea if this really works, but it wouldn't be difficult for you to set it up for a quick test
  • you prepare a simple function in RAM and jump with the M4 to it
  • in this function you flush all relevant pipelines in the M4 before you execute WFI()
  • with the M0APP you replace the code at this RAM location. When you wake the M4 up, you have at this program counter location again executable code, but now a new one.

Regards,

Bernhard.

[gertvierman]

Hi Bernhard,

Thanks for your answer, and sorry for my late reply.

I got this to work as I wanted. My first implementation used a kind of trampoline outside of the memory I wanted to replace; I kept the M4 in a tight loop there while replacing the code, and then let it jump out of the loop when ready. That worked.

Later I tried to simplify stuff, and I found out that issueing a M4 core reset in RESET_CTRL just works:

LPC_RGU->RESET_CTRL[RGU_M3_RST >> 5]

does *not* remap the boot ROM to address 0 and does the job  for me.

(Funny though, that the header files still call it 'M3_RST' instead of 'M4_RST')

[bernhardfink]

Thanks for the information, Gerd.

Interesting that this keeps the current PC of the core in place. We should reflect this somehow in our docu.

LPC1800 and LP4300 share mostly the same code base, that's why M3_RST is kept.

Regards,

Bernhard.

[jeremyzhou]

Hi,

Thank you for your interest in NXP Semiconductor products and 

for the opportunity to serve you.

I think the implementation is unavailable, the RAM is not the option of boot mode.

Have a great day,

TIC

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