void DMA3_transfer_from_SSP0_to_buffer(u8 count){ LPC_SC->DMAREQSEL = 0;//SC_DMASEL_timer0_MATCH1_notUART0rx;//i.V.m. DMAC_SRC_PERIP(9)LPC_GPDMACH0->DMACCConfig LPC_SC->PCONP |= (1<<29);//Enable clock to DMA controller LPC_GPDMA->DMACConfig=DMAC_CTRL_ENABLE; LPC_SSP0->DMACR=SSPxTxDMAenable;// ->DMACR=2;//tx en//176x LPC_GPDMACH3->DMACCSrcAddr = &(LPC_SSP0->DR); LPC_GPDMACH3->DMACCDestAddr = buffer+4; LPC_GPDMACH3->DMACCControl =(0 |DMAC_CHAN_INT_TC_EN // |DMAC_CHAN_SRC_AUTOINC |DMAC_CHAN_SRC_WIDTH_8 |DMAC_CHAN_SRC_BURST_1 |DMAC_CHAN_DEST_AUTOINC |DMAC_CHAN_DEST_WIDTH_8 |DMAC_CHAN_DEST_BURST_1 |DMAC_CHAN_TRANSFER_SIZE(count) ); LPC_GPDMACH3->DMACCConfig =(0 | DMA_CHAN_IE_ITC_EN // | DMAC_CHAN_FLOW_D_M2M // | DMAC_CHAN_FLOW_D_M2P //!!!!!!!!!!!!!! ?????????????? | DMAC_CHAN_FLOW_D_P2M | DMAC_SRC_PERIP(DMA_REQUEST_SSP0_TX) // | DMAC_SRC_PERIP(9) // | 1<<1//DMAC_SRC_PERIP(DMA_REQUEST_SSP0_RX) // | DMAC_DEST_PERIP(DMA_REQUEST_SSP0_TX) // | DMAC_DEST_PERIP(DMA_REQUEST_SSP0_RX) ); } |