Problem with SPI SCLK
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi!,
Firstly, I want to say hellow to everyone because it is my first question in this forum. Thank you to everyone.
I want to use a SPI connection with the LPC824 but the problem is that although CPOL and CPHA are set to 0, the SCLK starts at low state but then, before y send a byte, it mantains a high state.
I let you the SPI startup code below:
///spi
Init_SPI_PinMux();
Chip_GPIO_Init(LPC_GPIO_PORT);
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT,0,PIN_psel);
Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT,0,PIN_busy);
Chip_GPIO_SetPinDIRInput(LPC_GPIO_PORT,0,PIN_irq);
Chip_GPIO_SetPinState(LPC_GPIO_PORT,0,PIN_psel,true);
Chip_SPI_Init(LPC_SPI1);
Chip_SPI_ConfigureSPI(LPC_SPI1, SPI_MODE_MASTER | /* Enable master/Slave mode */
SPI_CLOCK_CPHA0_CPOL0 | /* Set Clock polarity to 0 */
SPI_CFG_MSB_FIRST_EN |/* Enable MSB first option */
SPI_CFG_SPOL_LO); /* Chipselect is active low */
Chip_SPI_Enable(LPC_SPI1);
Chip_SPI_ClearStatus(LPC_SPI1, SPI_STAT_CLR_RXOV | SPI_STAT_CLR_TXUR | SPI_STAT_CLR_SSA | SPI_STAT_CLR_SSD);
Chip_SPI_SetControlInfo(LPC_SPI1, 8, SPI_TXCTL_ASSERT_SSEL | SPI_TXCTL_EOF | SPI_TXCTL_RXIGNORE);
LPC_SPI1->DIV=0;
Thank you
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Finally, I could found the problem. I have to set the End Of Transfer Bit before each byte transfer.
![](/skins/images/62839796CFB79A3799B9CA130F0202DC/responsive_peak/images/icon_anonymous_message.png)