Phase locked loop

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Phase locked loop

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Senior Contributor I

Has anyone tried to make a phase locked loop out of one of the SCT timer? Has anyone succeeded?

I'd like to make SCT0 run in sync with the mains, because using the comparators as zero-cross detectors isn't that great on a noisy mains supply.

I tried computing the phase difference as SIN(2*PI*COUNT/MATCHREL)*COS(sampled input)-COS(2*PI*COUNT/MATCHREL)*SIN(sampled input) and then using the phase difference to adjust MATCHREL, but I can't get it to lock.

Any ideas? Is my sample rate (1600Hz) too low, or is the latency due to the period only updating after the next LIMIT event too long?

(The input is already a sinewave from the mains, and the cosine is found by taking a sample from quarter of a cycle ago.)

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NXP TechSupport
NXP TechSupport

Hi Ian Benton ,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Actually, I'm not very clear with your purpose, so I was wondering if you can introduce the scheme in details.

Have a great day,
TIC

 

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Senior Contributor I
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NXP TechSupport
NXP TechSupport

Hi Ian Benton,

Thanks for your reply.

I was wondering if you can share a compile-able demo which can replicate the phenomenon, it can help me to figure it out.

Looking forward to your reply.


Have a great day,
TIC

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Senior Contributor I

My guess is that there could be two possibilities:
1) The mains sinewave has enough distortion that the result of the calculation never equals zero, even when the two signals are in phase.

2) There is too much latency due to MATCHREL only updating MATCH when the counter "limits".

I'll spend some more time experimenting, and possibly try a signal generator instead of the mains reference.

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