#include "chip.h"
/**
* @briefHandle interrupt from State Configurable Timer
* @returnNothing
*/
void SCT0_1_IRQHandler(void)
{
/* Clear the Interrupt */
volatile uint32_t flag = Chip_SCT_GetEventFlag(LPC_SCT0);
if(flag & SCT_EVT_0)
{
LPC_SCT0->EVFLAG = SCT_EVT_0;
//Chip_GPIO_SetPinState(LPC_GPIO, 2, 2, 1);// NECESSARY?
}
if(flag & SCT_EVT_1)
{
LPC_SCT0->EVFLAG = SCT_EVT_1;
//Chip_GPIO_SetPinState(LPC_GPIO, 2, 2, 0);// NECESSARY?
}
if(flag & SCT_EVT_3)
{
LPC_SCT0->EVFLAG = SCT_EVT_3;
}
}
void SCT0_Init(void)
{
// enable clock for SCT0
Chip_SCT_Init(LPC_SCT0);
Chip_IOCON_PinMuxSet(LPC_IOCON, 2, 2, 0x00000083); // PIO2_2 as SCT0_OUT1
Chip_IOCON_PinMuxSet(LPC_IOCON, 1,13, 0x00000082); // PIO1_13 as SCT0_OUT3
// Chip_GPIO_SetPinDIROutput(LPC_GPIO, 2, 2); // Set as output pin - should not be necessary
// Chip_GPIO_SetPinDIROutput(LPC_GPIO, 1,13); // Set as output pin - should not be necessary
Chip_SCT_Init(LPC_SCT0); // Enable clock for SCT0/1
Chip_SCT_Config(LPC_SCT0, SCT_CONFIG_32BIT_COUNTER | SCT_CONFIG_AUTOLIMIT_L);// two 16-bit timers, clocked internally, auto limit
Chip_SCT_SetControl(LPC_SCT0, SCT_CTRL_PRE_L(24)); // Prescaler = 24@Core=48M => SCT clock = 2 MHz
Chip_SCT_SetMatchCount (LPC_SCT0, SCT_MATCH_0, 1000); // match 0 @ 10/2MHz = 5 usec (100 KHz PWM freq)
Chip_SCT_SetMatchReload(LPC_SCT0, SCT_MATCH_0, 1000);
Chip_SCT_SetMatchCount (LPC_SCT0, SCT_MATCH_1, 600); // match 1 used for duty cycle
Chip_SCT_SetMatchReload(LPC_SCT0, SCT_MATCH_1, 600);
Chip_SCT_SetMatchCount (LPC_SCT0, SCT_MATCH_3, 300); // match 3 used for duty cycle
Chip_SCT_SetMatchReload(LPC_SCT0, SCT_MATCH_3, 300);
Chip_SCT_EventState(LPC_SCT0, SCT_EVENT_0, ENABLE_STATE0);// event 0 only happens in state 0
Chip_SCT_EventControl(LPC_SCT0, SCT_EVENT_0, (CHIP_SCT_EVENTCTRL_T) ( SCT_EVECTRL_MATCH0 |// related to match 0
SCT_COMBMODE_MATCH|// COMBMODE[13:12] = match condition only
SCT_STATELD_1 |// STATELD[14] = STATEV is loaded into state
SCT_STATEEV_0 ));// STATEV[15] = 0
Chip_SCT_EventState(LPC_SCT0, SCT_EVENT_1, ENABLE_STATE0);// event 1 only happens in state 0
Chip_SCT_EventControl(LPC_SCT0, SCT_EVENT_1, (CHIP_SCT_EVENTCTRL_T) ( SCT_EVECTRL_MATCH1 |// related to match 1
SCT_COMBMODE_MATCH|// COMBMODE[13:12] = match condition only
SCT_STATELD_1 |// STATELD[14] = STATEV is loaded into state
SCT_STATEEV_0 )); // STATEV[15] = 0
Chip_SCT_EventState(LPC_SCT0, SCT_EVENT_3, ENABLE_STATE0);// event 3 only happens in state 0
Chip_SCT_EventControl(LPC_SCT0, SCT_EVENT_3, (CHIP_SCT_EVENTCTRL_T) ( SCT_EVECTRL_MATCH1 | // related to match 1
SCT_COMBMODE_MATCH|// COMBMODE[13:12] = match condition only
SCT_STATELD_1 |// STATELD[14] = STATEV is loaded into state
SCT_STATEEV_0 ));// STATEV[15] = 0
Chip_SCT_SetOutput(LPC_SCT1, SCT_OUTPUT_1, SCT_EVT_0);// event 0 will set SCTx_OUT0
Chip_SCT_ClearOutput(LPC_SCT1, SCT_OUTPUT_1, SCT_EVT_1);// event 1 will clear SCTx_OUT0
Chip_SCT_SetOutput (LPC_SCT0, SCT_OUTPUT_3, SCT_EVT_0);// event 0 will clear SCT_OUT3
Chip_SCT_ClearOutput(LPC_SCT0, SCT_OUTPUT_3, SCT_EVT_3);// event 3 will set SCT_OUT3
/* Enable an Interrupt on the Match Event */
Chip_SCT_EnableEventInt(LPC_SCT0, SCT_EVT_0);
Chip_SCT_EnableEventInt(LPC_SCT0, SCT_EVT_1);
Chip_SCT_EnableEventInt(LPC_SCT0, SCT_EVT_3);
/* Enable the IRQ for the SCT */
NVIC_EnableIRQ(SCT0_1_IRQn);
// unhalt it by clearing bit 2 of the CTRL register
Chip_SCT_ClearControl(LPC_SCT0, SCT_CTRL_HALT_L);
}
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