NXP LPC55S28JBD64K SPI - How to Reduce the Receiving SPI byte to Byte interval

[SimK]

Hi ,

Help needed, i need to perform a usb burst of a stream of high speed usb of 1024 byte of data through spi. However i do notice the receiving SPI byte byte 2 byte interval takes up about +-500ns.

Can we further reduce the receiving byte 2 byte interval? which is currently being measured at +-/ 500ns.

i have configured my SPI as follows:

SPI Speed = 48mhz
SPI Configuration as follows, for Flexcomm 0;

[SimK]

thanks for the quick reply.

I think i have set the max FIFO to accept 16bit, is it the same as you mentioned by changing TXLVL/RXLVL as 7? if not can guide me how to change those? 

or any example code that i can refer for SPI transfer without using the SPI SDK as my first SPI development. 

thanks.

[xiangjun_rong]

Hi,

They are not the same thing, as you know that the SPI has 8 entry FIFO for both transmitter and receiver, each FIFO can save 32 bits data including 16 bits data and the other control bits.

Pls refer to Table 683. FIFO write data register (FIFOWR - offset = 0xE20) in UM11126.pdf

35.6.15 FIFO write data register
The FIFOWR register is used to write values to be transmitted to the FIFO.
FIFOWR provides the possibility of altering some SPI controls at the same time as
sending new data. For example, this can allow a series of SPI transactions involving
multiple slaves to be stored in a DMA buffer and sent automatically.These added fields
are described for bits 16 through 27 below.
Each FIFO entry holds data and associated control bits. Before data and control bits are
pushed into the FIFO, the control bit settings can be modified. half-word writes to just the
control bits (offset 0xE22) and does not push anything into the FIFO. A 0 written to the
upper half-word will not modify the control settings. Non-zero writes to it will modify all the
control bits. This is a write only register. Do not read-modify-write the register.
Byte, half-word or word writes to FIFOWR will push the data and control bits into the FIFO.
Word writes with the upper half-word of 0, byte writes or half-word writes to FIFOWR will
push the data and the current control bits, into the FIFO. Word writes with a non-zero
upper half-word will modify the control bits before pushing them onto the stack.
To set-up a slave SPI for receive only, the control bit settings must be pushed into the
write FIFO to become active. Therefore, at least one write to the FIFOWR data bits must
be done to make the control bits active

For your case, as I said that the SDK driver is inefficient, if you want to reduce the interval between two transfer, you have to write the spi register yourself.

Hope it can help you

BR

XiangJun Rong

[xiangjun_rong]

Hi,

As you know that there is a delay register, which has 4 delay items, you set them all 0. So the delay configuration is correct, there is not improvement space.

Regarding the delay between two transfer you have observed, I suppose that it may be resulted from the cause that  the SPI transmitter FIFO data is not ready when the first two bytes data has completed or SDK driver inefficiency.

You can enable the FIFO mode and set the TXLVL/RXLVL as 7, so in the ISR of SPI, you can push 7 half-words to the WRFIFO, pls have a try.

If you pursue speed, I suggest you do not use the spi SDK driver, you can write register directly and use interrupt mode, the SPI SDK driver is inefficient.

Hope it can help you

BR

XiangJun Rong