MRT period in repeated interrupt mode?

[alexeyborisenko]

From user guide:

When the timer n is in idle state, writing a non-zero value IVALUE to the INTVALn register
immediately loads the time interval value IVALUE - 1, and the timer begins to count down
from this value. When the timer reaches zero, an interrupt is generated, the value in the
INTVALn register IVALUE - 1 is reloaded automatically, and the timer starts to count down
again.

Too many words here, but how exactly to calculate period T of generated interupt sequence for given IVALUE ?

T= IVALUE?

T=IVALUE-1?

T=IVALUE+1?

It is not clear from all words spent above.

[alexeyborisenko]

I'm using LPC812. It may bevave differently on different chips?

Thank you for support.

[kerryzhou]

Hi Alexey,

   Thank you for your patient, I have tested it on my side, and double check it with our according department colleagues.

   The precise T still should calculate with IVALUE-1,suppose IVALUE=4, the counter should be:

3,2,1,0, but take care, counter down from 3, so the actually time is just 3. 3 intervals.

    In your practical usage, please -1, but official code is still use the IVALUE, I think it is not precise enough, but just Hz frequency can't detect errors between IVALUE-1 or IVALUE.

Have a great day,
Kerry

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[alexeyborisenko]

I can't understand what you want to say.

When I say  timer counts:   ...3,2,1,0,3,2,1,0,3,2,1,0,... , this means each comma corresponds to exactly one clock  transition, and digit is timer value observed if read operation occurs within that clock. It is logically clear that period of this sequence is exactly 4 clocks. What you are meaning when saying T=3 in this sequence?

Maybe, this means that counter works as  ... ,u,2,1,u,2,1,u,2,1, ...  where "u" have no exact stable value, but most probably reads as either 0 or 3 ?

[kerryzhou]

Hi Alexey,

   Thank you for your updated information.

   This is my understanding:

Please note, when the timer reaches zero, at the same time, it loads IVALUE-1, not 0-1=IVALUE-1.

Please see the above picture: 3,2,1,0

Take care, 0->another 3, no 1 MRT clock, 0=3, it is at the same time, that's why I told you T=3 before.From the user manual description, you also can see it.Manual didn't say, when reach 0, go on count down to load IVALUE-1.

Wish it helps to you, if you still have question about it, please kindly let me know!

Have a great day,
Kerry

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[kerryzhou]

Hi Alexey Borisenko,

    From the user manual description, the precise T should be IVALUE-1.

Wish it helps you!

Have a great day,
Kerry

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[alexeyborisenko]

You really deduced it from user manual description? How?.

First, try answer to two questions:

Q1: Is there one-clock lag between timer approach zero and loading IVALUE-1?.

Q2: Is there one-clock lag between loading IVALUE-1 and first count-down?.

It is usual to suspect that one-clock lag may be present or not In Q1,Q2 or both.

But nothing stated in user guide about those lags, therefore it is most logically staigtforward to assume they absent.

Depending on answers for Q1, Q2, timer will behaves differently:

suppose IVALUE=4:

C1: no,no:      ...2,1,2,1,2,1...  T=IVALUE-2   (most straightforfard logical deduction from user guide statements)

C2: yes.no:    ...2,1,0,2,1,0,2,1,0...  T=IVALUE-1

C3: no,yes:    ...3,2,1,3,2,1,3,2,1...   T=IVALUE-1

C4: yes,yes:  ...3,2,1,0,3,2,1,0,3,2,1,0... T=IVALUE  ( most convenient behavior for timer)

So, If you deduced you answer from same user guide I have, it probably incorrect and can't help me.

And if your answer is really correct, I also still need to know which case is true: C2 or C3.

[kerryzhou]

Hi Alexey,

   Please tell me what the chip you are using? Please tell me the part number.

  I will use the test result to prove it, test is more useful than the deduction.In my memory, I have tested it before, but I will test it again, to double check it.

Have a great day,
Kerry

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