Long time LPC2k user getting started with LPC4337

[baldur]

Hello, long time (10+ years) user of LPC2100 and LPC2300 series here, and I'm starting a new project based on the LPC4300 series. Currently using a dev board with LPC4337 LQFP144 chip which I've set up my build environment for, written boot code and linker script and have it running code on single core now with interrupts.

I have some concerns which I haven't found answered in any of the documentation I've read so far.

One, for the time being I'm using Flash Magic until I've managed to port my custom boot loader to this platform, and Flash Magic for some dumb reason has an option to select which flash bank to write to. This is very counter intuitive as the hex file specifies where to place each and every byte it contains. Am I right in thinking this option has no effect whatsoever unless I have Flash Magic generate the boot vector checksum for me, in which case this option tells it where to place the checksum?

Two, what is the expected flash fetch time when the flash accelerator misses?

Three, with the two flash banks (A/B) being separated as they are, is one bank available for access during erase operations on the other bank?

Four, implementation wise, what is the bandwidth of the AHB layer? How does it cope with two cores running at the same time? Are the cores able to run at full speed as long as they're not accessing the same flash banks and same RAM banks? Does switching on the M0 core automatically have any implicit performance effect on the M4 core?

Five, does the LPC4337 or does it not provide the USB ROM API? User manual states "The USB ROM API is available on parts LPC4350/30/20 and LPC43S50/S30/S20." and does not include the 4337 in that list. However the sample code provided in lpc4337.zip distributed with the LPCxpresso IDE has examples using the USB ROM API.

Six, since the Cortex M4 does not provide two separate interrupt channels, IRQ and FIQ, I may need to use nested interrupts in my application. On the LPC2000 series I managed to avoid interrupt nesting by using the FIQ to handle the one interrupt that was jitter sensitive. Are there any code examples available showing the use of nested interrupts on the LPC4000/Cortex M4 platform?

[soledad · Accepted solution]

Hi,

Please check my comments below:

1. Yes, you are correct.

2. Need to verify.

3. No there is only one physical memory, with two logical banks 

4. I do not have a good answer for your questions, lets said that it is just like traffic in a highway, depends on how much use it is going to be in both lines, if one has a big truck but the other has a bus,  the bus it is going to have much time the line instead of the truck or a car. It is difficult to said.

The main idea to have both cores it is to have a principal core running with the master code, and just to have a dummy core doing small tasks.  To give you an example only one core it is the one to boot, the second waits until the first one gives the order to boot the second one.

5. Yes it is the same.

6. Need to verify.

Have a great day,
Sol

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[baldur]

Thank you for your answer.

For #2 I have actually figured that one out from reading into the user manual, where it states at maximum clock frequency, 10 clock cycles are required for reliably executing a dry read from a flash address, allowing a random read rate of 20.4MHz. This is only barely faster than the LPC2300 which needs 4 clock cycles to execute a read at 72MHz allowing a random read rate of 18MHz.

I guess I will need to write some benchmarks to find out how the two cores coexist and what kind of performance penalty the M4 core takes when the M0 core starts running. It may make sense to have the M0 simply sleep when it's not running an interrupt.

It is really too bad if the entire 1MB flash memory is unavailable during a single block erase cycle that takes forever (hundreds of milliseconds) to execute. I have more data than I can easily fit in RAM and being able to page it in and out of flash while the system is running is necessary. I would very much like to be able to do this without shutting the system down for the duration of the flash erase. Maybe a workaround is to keep the most critical interrupts in RAM and only block interrupts of lower priority during erase.