LPC8xx USART synchronous mode SCLK edge

[johanmyréen]

My question is about the USART module in the LPC8xx series microcontrollers. If the USART is transmitting in synchronous mode, does the signal transition on the rising or falling edge of SCLK, i.e. should the receiver sample it on the falling or rising edge of SCLK? I can't find this information in the User's Guide. The guide mentions CLKPOL (bit 12 in the USART config register), which determines the clock edge used by the receiver. Does this bit also affect the transmitter, or is there some other way of selecting the edge? If CLKPOL also affects the transmitter, I would assume the signal transition would happen on the opposite edge, so that similarly configured devices could communicate with each other.

[kerryzhou · Accepted solution]

Hi Johan,

  1. If the USART is transmitting in synchronous mode, does the signal transition on the rising or falling edge of SCLK,

   You can find the according information in the datasheet.

     You can find, when UART is transmitting, it still determined by the CLKPOL.

1. CLKPOL=0, rising is changing data, falling is acquiring data.

2. CLKPOL=1, falling is changing data, rising is acquiring data.

The USART timing is very clear.

Wish it helps you!

If you still have question, please let me know!

Have a great day,
Kerry

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[johanmyréen]

Thank you for your answer. Mmy fault, I didn't think of looking for this information in the data sheet, only the User Manual. The User Manual is incomplete: it does document the CLKPOL bit, but only for received data. It doesn't say that the CLKPOL bit also applies to transmitted data, or on which edge the data is safe to sample.

All is clear now, thank you once again for your help.